Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology. - Zeynep Toprak Deniz; Yusuf Leblebici (ISCAS (1), 2003)

Low-power current mode logic for improved DPA-resistance in embedded systems. - Zeynep Toprak Deniz; Yusuf Leblebici (ISCAS (2), 2005)

Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation. - Zeynep Toprak Deniz; Yusuf Leblebici; Eric A. Vittoz (VLSI-SoC, 2006)

A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. - Francesco Regazzoni 001; Stéphane Badel; Thomas Eisenbarth 001; Johann Großschädl; Axel Poschmann; Zeynep Toprak Deniz; Marco Macchetti; Laura Pozzi 001; Christof Paar; Yusuf Leblebici; Paolo Ienne (ICSAMOS, 2007)

On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation. - Zeynep Toprak Deniz; Yusuf Leblebici; Eric A. Vittoz (IEEE J. Solid State Circuits, 2007)

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology. - Thomas Liechti; Armin Tajalli; Omer Can Akgun; Zeynep Toprak Deniz; Yusuf Leblebici (APCCAS, 2008)

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS. - John F. Bulzacchelli; Timothy O. Dickson; Zeynep Toprak Deniz; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Sergey V. Rylov; Daniel J. Friedman (ISSCC, 2009)

Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. - Alexander V. Rylyakov; José A. Tierno; Herschel A. Ainspan; Jean-Olivier Plouchart; John F. Bulzacchelli; Zeynep Toprak Deniz; Daniel J. Friedman (ISSCC, 2009)

Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. - Francesco Regazzoni 001; Thomas Eisenbarth 001; Axel Poschmann; Johann Großschädl; Frank K. Gürkaynak; Marco Macchetti; Zeynep Toprak Deniz; Laura Pozzi 001; Christof Paar; Yusuf Leblebici; Paolo Ienne (Trans. Comput. Sci., 2009)

A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS. - Jean-Olivier Plouchart; Mihai A. T. Sanduleanu; Zeynep Toprak Deniz; Troy J. Beukema; Scott K. Reynolds; Benjamin D. Parker; Michael P. Beakes; José A. Tierno; Daniel J. Friedman (CICC, 2012)

Root cause identification of an hard-to-find on-chip power supply coupling fail. - Franco Stellari; Thomas Cowell; Peilin Song; Michael Sorna; Zeynep Toprak Deniz; John F. Bulzacchelli; Nandita A. Mitra (ITC, 2012)

Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage. - John F. Bulzacchelli; Zeynep Toprak Deniz; Todd M. Rasmus; Joseph A. Iadanza; William L. Bucossi; Seongwon Kim; Rafael Blanco; Carrie E. Cox; Mohak Chhabra; Christopher D. LeBlanc; Christian L. Trudeau; Daniel J. Friedman (IEEE J. Solid State Circuits, 2012)

The POWER8TM processor: Designed for big data, analytics, and cloud environments. - Joshua Friedrich; Hung Q. Le; William J. Starke; Jeff Stuecheli; Balaram Sinharoy; Eric J. Fluhr; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; David Hogenmiller; Frank Malgioglio; et al. (ICICDT, 2014)

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. - Zeynep Toprak Deniz; Michael A. Sperling; John F. Bulzacchelli; Gregory S. Still; Ryan Kruse; Seongwon Kim; David Boerstler; Tilman Gloekler; Raphael Robertazzi; Kevin Stawiasz; Tim Diemoz; George English; et al. (ISSCC, 2014)

5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. - Eric J. Fluhr; Joshua Friedrich; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; Allen Hall; David Hogenmiller; Frank Malgioglio; Ryan Nett; Jose Paredes; Juergen Pille; et al. (ISSCC, 2014)

A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. - Timothy O. Dickson; Yong Liu 023; Ankur Agrawal; John F. Bulzacchelli; Herschel A. Ainspan; Zeynep Toprak Deniz; Benjamin D. Parker; Mounir Meghelli; Daniel J. Friedman (CICC, 2015)

IBM POWER8 circuit design and energy optimization. - Victor V. Zyuban; Joshua Friedrich; Daniel M. Dreps; Jürgen Pille; Donald W. Plass; Phillip J. Restle; Zeynep Toprak Deniz; Matthew M. Ziegler; Sam G. Chu; Md. Saiful Islam 004; James D. Warnock; Bob Philhower; et al. (IBM J. Res. Dev., 2015)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. - Sergey V. Rylov; Troy J. Beukema; Zeynep Toprak Deniz; Thomas Toifl; Yong Liu 023; Ankur Agrawal; Peter Buchmann; Alexander V. Rylyakov; Michael P. Beakes; Benjamin D. Parker; Mounir Meghelli (ISSCC, 2016)

A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. - Timothy O. Dickson; Yong Liu 023; Ankur Agrawal; John F. Bulzacchelli; Herschel A. Ainspan; Zeynep Toprak Deniz; Benjamin D. Parker; Michael P. Beakes; Mounir Meghelli; Daniel J. Friedman (IEEE J. Solid State Circuits, 2016)

A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. - Jonathan E. Proesel; Zeynep Toprak Deniz; Alessandro Cevrero; Ilter Özkaya; Seongwon Kim; Daniel M. Kuchta; Sungjae Lee 005; Sergey V. Rylov; Herschel A. Ainspan; Timothy O. Dickson; John F. Bulzacchelli; Mounir Meghelli (IEEE J. Solid State Circuits, 2018)

Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14nm SOI CMOS. - Miguel E. Perez; Michael A. Sperling; Timothy E. Diemoz; John F. Bulzacchelli; Zeynep Toprak Deniz (CICC, 2019)

A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS. - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (ISSCC, 2019)

A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS. - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (IEEE J. Solid State Circuits, 2020)

Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS". - Zeynep Toprak Deniz; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Timothy O. Dickson; Michael P. Beakes; Mounir Meghelli (IEEE J. Solid State Circuits, 2020)

Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS. - Miguel E. Perez; Michael A. Sperling; John F. Bulzacchelli; Zeynep Toprak Deniz; Timothy E. Diemoz (IEEE J. Solid State Circuits, 2020)

SE4: ICs in PandemICs. - Negar Reiskarimian; Zeynep Toprak Deniz; Ulkuhan Guler 001; Kathy Wilcox; Alice Wang; Jane Gu; Yaoyao Jia; Alicia Klinefelter; Rikky Muller; Farhana Sheikh; Yildiz Sinangil; Trudy Stetzler; et al. (ISSCC, 2021)

A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Troy J. Beukema; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (VLSI Technology and Circuits, 2022)

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. - Serdar S. Yonar; Pier Andrea Francese; Matthias Brändli; Marcel A. Kossel; Thomas Morf; Jonathan E. Proesel; Sergey V. Rylov; Herschel A. Ainspan; Martin Cochet; Zeynep Toprak Deniz; Timothy O. Dickson; Troy J. Beukema; et al. (VLSI Technology and Circuits, 2022)

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Troy J. Beukema; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (IEEE J. Solid State Circuits, 2023)

Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; John F. Bulzacchelli; Marcel A. Kossel; Pier Andrea Francese; Thomas Morf; Jonathan E. Proesel; Herschel A. Ainspan; Matthias Brändli; Mounir Meghelli (CICC, 2024)

A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1 mathrm{V}_{ text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS. - Zeynep Toprak Deniz; Timothy O. Dickson; Martin Cochet; Jonathan E. Proesel; John F. Bulzacchelli; Herschel A. Ainspan; Matthias Brändli; Thomas Morf; Michael P. Beakes; Mounir Meghelli (VLSI Technology and Circuits, 2024)