3D Reservoir Computing with High Area Efficiency (5.12 TOPS/mm2) Implemented by 3D Dynamic Memristor Array for Temporal Signal Processing. - Wenxuan Sun; Woyu Zhang; Jie Yu 027; Yi Li 049; Zeyu Guo 002; Jinru Lai; Danian Dong; Xu Zheng; Fei Wang; Shaoyang Fan; Xiaoxin Xu; Dashan Shang; et al. (VLSI Technology and Circuits, 2022)

Few-shot graph learning with robust and energy-efficient memory-augmented graph neural network (MAGNN) based on homogeneous computing-in-memory. - Woyu Zhang; Shaocong Wang; Yi Li 049; Xiaoxin Xu; Danian Dong; Nanjia Jiang; Fei Wang; Zeyu Guo 002; Renrui Fang; Chunmeng Dou; Kai Ni; Zhongrui Wang; et al. (VLSI Technology and Circuits, 2022)

Mixed-Precision Continual Learning Based on Computational Resistance Random Access Memory. - Yi Li 049; Woyu Zhang; Xiaoxin Xu; Yifan He 003; Danian Dong; Nanjia Jiang; Fei Wang; Zeyu Guo 002; Shaocong Wang; Chunmeng Dou; Yongpan Liu; Zhongrui Wang; et al. (Adv. Intell. Syst., 2022)

An ADC-Less RRAM-Based Computing-in-Memory Macro With Binary CNN for Efficient Edge AI. - Yi Li 049; Jia Chen; Linfang Wang; Woyu Zhang; Zeyu Guo 002; Jun Wang; Yongkang Han; Zhi Li 070; Fei Wang; Chunmeng Dou; Xiaoxin Xu; Jianguo Yang; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

IG-CRM: Area/Energy-Efficient IGZO-Based Circuits and Architecture Design for Reconfigurable CIM/CAM Applications. - Zeyu Guo 002; Jinshan Yue; Shengzhe Yan; Zhuoyu Dai; Xiangqu Fu; Zhaori Cong; Zening Niu; Ke Hu; Lihua Xu; Jiawei Wang; Lingfei Wang; Guanhua Yang; et al. (DAC, 2024)

A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications. - Zhuoyu Dai; Shengzhe Yan; Zhaori Cong; Zeyu Guo 002; Yifan He 002; Wenyu Sun; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Yongpan Liu; Ming Liu 022 (VLSI Technology and Circuits, 2024)

A monolithic 3D IGZO-RRAM-SRAM-integrated architecture for robust and efficient compute-in-memory enabling equivalent-ideal device metrics. - Shengzhe Yan; Zhaori Cong; Zi Wang; Zhuoyu Dai; Zeyu Guo 002; Zhihang Qian; Xufan Li; Xu Zheng; Chuanke Chen; Nianduan Lu; Chunmeng Dou; Guanhua Yang; et al. (Sci. China Inf. Sci., 2025)

An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet. - Zhihang Qian; Shengzhe Yan; Zhuoyu Dai; Zeyu Guo 002; Zhaori Cong; Yifan He 002; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Yongpan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications. - Jun Wang; Shengzhe Yan; Xiangqu Fu; Zhihang Qian; Zhi Li 062; Zeyu Guo 002; Zhuoyu Dai; Zhaori Cong; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Dashan Shang (IEEE Trans. Very Large Scale Integr. Syst., 2025)