A low power 1.0 GHz VCO in 65nm-CMOS LP-process. - Zhang Zhang 004; Zhiyi Yu; Xu Cheng 002; Xiaoyang Zeng (ASICON, 2011)

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. - Jun Han 003; Xingxing Zhang; Yi Li; Baoyu Xiong; Yuejun Zhang; Zhang Zhang 004; Zhiyi Yu; Xu Cheng 002; Xiaoyang Zeng (IEICE Electron. Express, 2012)

Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS. - Pengjun Wang; Yuejun Zhang; Jun Han 003; Zhiyi Yu; Yibo Fan; Zhang Zhang 004 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Fast-Settling Feedforward Automatic Gain Control Based on a New Gain Control Approach. - Xin Cheng 001; Guangjun Xie; Zhang Zhang 004; Yizhong Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 16-Core Processor With Shared-Memory and Message-Passing Communications. - Zhiyi Yu; Ruijin Xiao; Kaidi You; Heng Quan; Peng Ou; Zheng Yu 001; Maofei He; Jiajie Zhang; Yan Ying; Haofan Yang 001; Jun Han 003; Xu Cheng 002; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. - Xiaoyang Zeng; Yi Li; Yuejun Zhang; Shujie Tan; Jun Han 003; Xingxing Zhang; Zhang Zhang 004; Xu Cheng 002; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A multi-core-based heterogeneous parallel turbo decoder. - Jianmin Zeng; Chubin Wu; Zhang Zhang 004; Xin Cheng 001; Guangjun Xie; Jun Han 003; Xiaoyang Zeng; Zhiyi Yu (IEICE Electron. Express, 2017)

An Output-Capacitorless Ultra-Low Power Low-Dropout Regulator. - Xin Cheng 001; Hongyu Liang; Longjie Du; Zhang Zhang 004; Maoxiang Yi; Guangjun Xie (J. Circuits Syst. Comput., 2017)

Study of High Voltage Deep Brain Stimulation. - Zhang Zhang 004; Lingling Wei; Xiaojuan Zhou; Taolue Zhu; Guangjun Xie; Xin Cheng 001 (APCCAS, 2018)

A Qi compatible wireless power receiver with integrated full-wave synchronous rectifier. - Chubin Wu; Zhang Zhang 004; Jianmin Zeng; Xin Cheng 001; Guangjun Xie (Sci. China Inf. Sci., 2018)

A 15 W wireless power receiver with an improved full-wave synchronous rectifier. - Chubin Wu; Guangjun Xie; Zhang Zhang 004; Xin Cheng 001; Tairan Fei; Jianmin Zeng; Xiaoyang Zeng (IEICE Electron. Express, 2018)

Countering power analysis attacks by exploiting characteristics of multicore processors. - Jianwei Yang; Fan Dai; Jielin Wang; Jianmin Zeng; Zhang Zhang 004; Jun Han 003; Xiaoyang Zeng (IEICE Electron. Express, 2018)

A Single-Input Multi-Output Piezoelectric Energy Harvesting System Combining with P-SSHI and Cold Startup Circuit. - Xin Cheng 001; Bo Cheng; Zechen Tang; Yongqiang Zhang 006; Zhang Zhang 004 (APCCAS, 2019)

A 30MHz Delay-Line-Based Buck Converter with 5.7%-94.8% Switching Duty Cycle. - Zhang Zhang 004; Shu Xu; Fangzhou Yao; Guangjun Xie; Xin Cheng 001 (APCCAS, 2019)

A Fast and Accurate Edge Detection Algorithm for Real-Time Deep-Space Autonomous Optical Navigation. - Hao Xiao; Yanming Fan; Zhang Zhang 004; Xin Cheng 001 (IDAACS, 2019)

A 24-bit sigma-delta ADC with configurable chopping scheme. - Li Li 038; Xu Cheng 002; Zhang Zhang 004; Jianmin Zeng; Xiaoyang Zeng (IEICE Electron. Express, 2019)

Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata. - Haotian Chen; Hongjun Lv; Zhang Zhang 004; Xin Cheng 001; Guangjun Xie (J. Circuits Syst. Comput., 2019)

High frequency and high efficiency DC-DC converter with sensorless adaptive-sizing technique. - Xin Cheng 001; Wanjing Shao; Yongqiang Zhang 006; Jianmin Zeng; Zhang Zhang 004 (IEICE Electron. Express, 2020)

DM-IMCA: A dual-mode in-memory computing architecture for general purpose processing. - Jianmin Zeng; Zhang Zhang 004; Runhao Chen; Shiyue Liang; Tianlin Cao; Zhiyi Yu; Xin Cheng 001; Guangjun Xie (IEICE Electron. Express, 2020)

Algorithm-Hardware Co-Design of Real-Time Edge Detection for Deep-Space Autonomous Optical Navigation. - Hao Xiao; Yanming Fan; Fen Ge; Zhang Zhang 004; Xin Cheng 001 (IEICE Trans. Inf. Syst., 2020)

CFE: a convenient, flexible, and efficient clocking scheme for quantum-dot cellular automata. - Feifei Deng; Guangjun Xie; Xin Cheng 001; Zhang Zhang 004; Yongqiang Zhang 006 (IET Circuits Devices Syst., 2020)

A High Resolution DPWM Based on Synchronous Phase-Shifted Circuit and Delay Line. - Xin Cheng 001; Wanjing Shao; Lixin Xu; Yongqiang Zhang 006; Guangjun Xie; Zhang Zhang 004 (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A Feedback Architecture of High Speed True Random Number Generator based on Ring Oscillator. - Xin Cheng 001; Haowen Zhu; Xinyi Xing; Yunfeng Zhang; Yongqiang Zhang 006; Guangjun Xie; Zhang Zhang 004 (A-SSCC, 2021)

A high-resolution hybrid digital pulse width modulator with dual-edge-triggered flip-flops and hardware compensation. - Xin Cheng 001; Bin Li; Haowen Zhu; Yongqiang Zhang 006; Zhang Zhang 004 (Int. J. Circuit Theory Appl., 2021)

An output capacitor-less low-dropout regulator with wide load capacitance and current ranges. - Zhang Zhang 004; Shu Xu; Hongyuan Wu; Guangjun Xie; Xin Cheng 001 (Int. J. Circuit Theory Appl., 2021)

A reconfigurable and compact hardware architecture of CLEFIA block cipher with multi-configuration. - Xin Cheng 001; Haowen Zhu; Yixuan Xu; Yongqiang Zhang 006; Hao Xiao; Zhang Zhang 004 (Microelectron. J., 2021)

Using correction parameters to improve real-time video interpolation in low-cost VLSI implementation. - Haowei Guan; Zhang Zhang 004; Xin Cheng 001; Yizhong Yang; Guangjun Xie (Microelectron. J., 2021)

A novel control circuit for piezoelectric energy harvesting. - Zhang Zhang 004; Zechen Tang; Zhang Yunfeng; Xin Cheng 001; Guangjun Xie (Microelectron. J., 2021)

Reconfigurable multivalued memristor FPGA model for digital recognition. - Zhang Zhang 004; Ao Xu; Hongtao Ren; Gang Liu; Xin Cheng 001 (Int. J. Circuit Theory Appl., 2022)

Mathematical analysis and circuit emulator design of the three-valued memristor. - Zhang Zhang 004; Ao Xu; Chao Li; Gang Liu; Xin Cheng 001 (Integr., 2022)

Gate-Controlled Memristor FPGA Model for Quantified Neural Network. - Zhang Zhang 004; Ao Xu; Chao Li; Yadong Wei; Zhiheng Ge; Xin Cheng 001; Gang Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

STPNet: A Spatial-Temporal Propagation Network for Background Subtraction. - Yizhong Yang; Jiahao Ruan; Yongqiang Zhang 006; Xin Cheng 001; Zhang Zhang 004; Guangjun Xie (IEEE Trans. Circuits Syst. Video Technol., 2022)

MSE-Net: generative image inpainting with multi-scale encoder. - Yizhong Yang; Zhihang Cheng; Haotian Yu; Yongqiang Zhang 006; Xin Cheng 001; Zhang Zhang 004; Guangjun Xie (Vis. Comput., 2022)

An FPGA-based memristor emulator for artificial neural network. - Zhang Zhang 004; Chao Li; Weiqi Zhang; Jing Zhou; Gang Liu (Microelectron. J., 2023)

Cascaded deep residual learning network for single image dehazing. - Yizhong Yang; Ce Hou; Haixia Huang; Zhang Zhang 004; Guangjun Xie (Multim. Syst., 2023)

A multi-scale inputs and labels model for background subtraction. - Yizhong Yang; Dajin Li; Xiang Li; Zhang Zhang 004; Guangjun Xie (Signal Image Video Process., 2023)

Lightweight and flexible hardware implementation of authenticated encryption algorithm SIMON-Galois/Counter Mode. - Xin Cheng 001; Yixuan Xu; Kefan Wang; Yongqiang Zhang 006; Bin Li; Zhang Zhang 004 (Int. J. Circuit Theory Appl., 2023)

A multi-scale feature fusion spatial-channel attention model for background subtraction. - Yizhong Yang; Tingting Xia; Dajin Li; Zhang Zhang 004; Guangjun Xie (Multim. Syst., 2023)

A 10T SRAM with Two Read and Write Modes across Row and Column for CAM Operation and Computing In-Memory. - Zhang Zhang 004; Zhihao Chen; Sikai Chen; Guangjun Xie; Jianmin Zeng; Gang Liu (ISCAS, 2024)

Cascaded refinement residual attention network for image outpainting. - Yizhong Yang; Shanshan Yao; Changjiang Liu; Zhang Zhang 004; Guangjun Xie (Multim. Syst., 2024)

A gate-tunable memristor emulator for motion detection. - Zhang Zhang 004; Yongbo Ma; Gang Shi; Chao Li; Gang Liu (Int. J. Circuit Theory Appl., 2024)

Voltage-Resistance-Adaptive MPPT Circuit for Energy Harvesting. - Zhang Zhang 004; Annan Wang; Hongtao Ren; Guangjun Xie; Xin Cheng 001 (IEEE Des. Test, 2024)

Memristor-Based Neural Network Circuit of Associative Memory With Occasion Setting. - Juntao Han; Xin Cheng 001; Guangjun Xie; Junwei Sun; Gang Liu; Zhang Zhang 004 (IEEE Trans. Cogn. Dev. Syst., 2024)

A Lightweight Authenticated Encryption Algorithm Based on Compact CLEFIA Block Cipher. - Meiyu Liang; Tao Ji; Yin Yuan; Xin Cheng 001; Zhang Zhang 004; Lixiang Ma (J. Circuits Syst. Comput., 2025)

A class-AB rail-to-rail operational amplifier with wide supply voltage and high gain. - Sikai Chen; Peng Zhang; Lumiao Zhang; Zhang Zhang 004 (Microelectron. J., 2025)

A 15.4 nW, 59 ppm/∘C CMOS voltage reference circuit with process and temperature compensation. - Annan Wang; Yuchen Sun; Zhang Zhang 004 (Microelectron. J., 2025)

Reconfigurable 10T SRAM for Energy-Efficient CAM Operation and In-Memory Computing. - Zhang Zhang 004; Zhihao Chen; Jiedong Wang; Guangjun Xie; Gang Liu (IEEE Trans. Very Large Scale Integr. Syst., 2025)