Effective capacitance for gate delay with RC loads. - Zhangcai Huang; Atsushi Kurokawa; Yasuaki Inoue (ISCAS (3), 2005)

A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads. - Zhangcai Huang; Atsushi Kurokawa; Yasuaki Inoue; Junfa Mao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew. - Zhangcai Huang; Atsushi Kurokawa; Jun Pan; Yasuaki Inoue (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. - Atsushi Kurokawa; Masanori Hashimoto; Akira Kasebe; Zhangcai Huang; Yun Yang; Yasuaki Inoue; Ryosuke Inagaki; Hiroo Masuda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A Wide Dynamic Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback. - Zhangcai Huang; Yasuaki Inoue; Hong Yu 013; Quan Zhang (APCCAS, 2006)

Behavioral macromodeling of analog LSI implementation for automobile intake system. - Zhangcai Huang; Yasuaki Inoue; Quan Zhang; Yuehu Zhou; Long Xie; Harutoshi Ogai (ISCAS, 2006)

An effective pseudo-transient algorithm for finding DC operating points of nonlinear circuits. - Hong Yu 013; Yasuaki Inoue; Yuki Matsuya; Zhangcai Huang (ISCAS, 2006)

Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay. - Zhangcai Huang; Atsushi Kurokawa; Yun Yang; Hong Yu 013; Yasuaki Inoue (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills. - Atsushi Kurokawa; Akira Kasebe; Toshiki Kanamoto; Yun Yang; Zhangcai Huang; Yasuaki Inoue; Hiroo Masuda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays. - Atsushi Kurokawa; Hiroo Masuda; Junko Fujii; Toshinori Inoshita; Akira Kasebe; Zhangcai Huang; Yasuaki Inoue (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

An Effective Pseudo-Transient Algorithm for Finding Dc Solutions of Nonlinear Circuits. - Hong Yu 013; Yasuaki Inoue; Yuki Matsuya; Zhangcai Huang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies. - Zhangcai Huang; Hong Yu 013; Atsushi Kurokawa; Yasuaki Inoue (ASP-DAC, 2007)

Behavioral Circuit Macromodeling and Analog LSI Implementation for Automobile Engine Intake System. - Zhangcai Huang; Yasuaki Inoue; Hong Yu 013; Jun Pan; Yun Yang; Quan Zhang; Shuai Fang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A Low-Power Sub-1-V Low-Voltage Reference Using Body Effect. - Jun Pan; Yasuaki Inoue; Zheng Liang; Zhangcai Huang; Weilun Huang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

An Effective SPICE3 Implementation of the Compound Element Pseudo-Transient Algorithm. - Hong Yu 013; Yasuaki Inoue; Kazutoshi Sako; Xiaochuan Hu; Zhangcai Huang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A Highly Linear and Wide Input Range Four-Quadrant CMOS Analog Multiplier Using Active Feedback. - Zhangcai Huang; Minglu Jiang; Yasuaki Inoue (IEICE Trans. Electron., 2009)

Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model. - Minglu Jiang; Zhangcai Huang; Atsushi Kurokawa; Shuai Fang; Yasuaki Inoue (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A CMOS Sub-l-V nanopower current and voltage reference with leakage compensation. - Zhangcai Huang; Qin Luo; Yasuaki Inoue (ISCAS, 2010)

A low voltage CMOS rectifier for wirelessly powered devices. - Qiang Li; Renyuan Zhang; Zhangcai Huang; Yasuaki Inoue (ISCAS, 2010)

Memristor Model for SPICE. - Xuliang Zhang; Zhangcai Huang; Juebang Yu (IEICE Trans. Electron., 2010)

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. - Zhangcai Huang; Atsushi Kurokawa; Masanori Hashimoto; Takashi Sato 001; Minglu Jiang; Yasuaki Inoue (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A sub-100nA power management system for wireless structure health monitoring applications. - Zhangcai Huang; Yasuaki Inoue (ISCAS, 2011)

A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect. - Minglu Jiang; Zhangcai Huang; Atsushi Kurokawa; Qiang Li; Bin Lin; Yasuaki Inoue (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model. - Gong Chen 002; Bo Yang 004; Shigetoshi Nakatake; Zhangcai Huang; Yasuaki Inoue (ISCAS, 2012)

Modeling the Overshooting Effect of Multi-Input gate in Nanometer Technologies. - Li Ding; Zhangcai Huang; Minglu Jiang; Atsushi Kurokawa; Yasuaki Inoue (J. Circuits Syst. Comput., 2012)

An analytical model of the overshooting effect for multiple-input gates in nanometer technologies. - Li Ding; Jing Wang; Zhangcai Huang; Atsushi Kurokawa; Yasuaki Inoue (ISCAS, 2013)

An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies. - Li Ding; Zhangcai Huang; Atsushi Kurokawa; Jing Wang; Yasuaki Inoue (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)