A high-speed, programmable, CSD coefficient FIR filter. - Zhangwen Tang; Jie Zhang; Hao Min (IEEE Trans. Consumer Electron., 2002)

Standard CMOS technology on-chip inductors with pn junctions substrate isolation. - Hongyan Jian; Zhangwen Tang; Jie He 003; Jinglan He; Min Hao (ASP-DAC, 2005)

An accurate 1.08-GHz CMOS LC voltage-controlled oscillator. - Zhangwen Tang; Jie He 003; Hongyan Jian; Hao Min (ASP-DAC, 2005)

Prediction of LC-VCOs' tuning curves with period calculation technique. - Zhangwen Tang; Jie He 003; Hongyan Jian; Haiqing Zhang; Jie Zhang; Hao Min (ASP-DAC, 2005)

A fully differential charge pump with accurate current matching and rail-to-rail common-mode feedback circuit. - Zhenyu Yang; Zhangwen Tang; Hao Min (ISCAS, 2008)

Comments on "Comments on "A General Theory of Phase Noise in Electrical Oscillators"". - Lei Lu; Zhangwen Tang; Pietro Andreani; Andrea Mazzanti; Ali Hajimiri (IEEE J. Solid State Circuits, 2008)

Author's Response. - Lei Lu; Zhangwen Tang; Pietro Andreani; Andrea Mazzanti; Ali Hajimiri (IEEE J. Solid State Circuits, 2008)

A sub-0.75°RMS-phase-error differentially-tuned fractional-N synthesizer with on-chip LDO regulator and analog-enhanced AFC technique. - Lei Lu; Lingbu Meng; Liang Zou; Hao Min; Zhangwen Tang (CICC, 2009)

A 975-to-1960MHz fast-locking fractional-N synthesizer with adaptive bandwidth control and 4/4.5 prescaler for digital TV tuners. - Lei Lu; Zhichao Gong; Youchun Liao; Hao Min; Zhangwen Tang (ISSCC, 2009)

A wideband CMOS variable-gain low noise amplifier with novel attenuator. - Tao Cheng; Tao Yang; Xin Wang 130; Zhangwen Tang (ASICON, 2013)

A 50-to-930MHz quadrature-output fractional-N frequency synthesizer with 770-to-1860MHz single-inductor LC-VCO and without noise folding effect for multistandard DTV tuners. - Zhangwen Tang; Xiongxiong Wan; Minggui Wang; Jie Liu (ISSCC, 2013)

PDK design of 0.13um SOI process. - Jiang Bingjian; Junli Sheng; Zhangwen Tang (ASICON, 2015)

A high PSR SOI current-mode bandgap reference. - Junli Sheng; Bingjian Jiang; Zhangwen Tang (ASICON, 2015)

Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors. - Changhai Liao; Jun Tao 001; Handi Yu; Zhangwen Tang; Yangfeng Su; Dian Zhou; Xuan Zeng 001; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A broadband power detector with temperature and process compensation. - Yifan Gao; Weigang Xu; Chenyang Kong; Zhangwen Tang (ASICON, 2017)

A 1.0-to-2.4GHz wideband VCO with uniform sub-band interval and constant tuning gain. - Chenyang Kong; Xiaodong Liu 018; Weigang Xu; Zhangwen Tang (ASICON, 2017)

A 0.07-ppm/step differential digitally controlled crystal oscillator with guaranteed monotonicity. - Xiaodong Liu 018; Chenyang Kong; Yifan Gao; Zhangwen Tang (ASICON, 2017)

A 18 mW 12 bit 50 MS/s SHA-less pipelined ADC. - Weigang Xu; Yifan Gao; Xiaodong Liu 018; Zhangwen Tang (ASICON, 2017)

A Synthesizable Constant Tuning Gain Technique for Wideband LC-VCO Design. - Xiaoxue Sun; Chenyang Kong; Yingyu Chen; Jun Tao 001; Zhangwen Tang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A complementary fully differential dynamic comparator with insensitive common-mode mismatch. - Yingyu Chen; Xiangcheng Liu; Zhangwen Tang; Jie He 003; Wei Hu (IEICE Electron. Express, 2022)

A 2.5-Vpp PVT-insensitive high dynamic range output stage using bulk voltages adjustment. - Xiangcheng Liu; Yingyu Chen; Zhangwen Tang (IEICE Electron. Express, 2022)