LORE: A loop repository for the evaluation of compilers. - Zhi Chen 001; Zhangxiaowen Gong; Justin Josef Szaday; David C. Wong 001; David A. Padua; Alexandru Nicolau; Alexander V. Veidenbaum; Neftali Watkinson; Zehra Sura; Saeed Maleki; Josep Torrellas; Gerald DeJong (IISWC, 2017)

Using Hardware Counters to Predict Vectorization. - Neftali Watkinson; Aniket Shivam; Zhi Chen 001; Alexander V. Veidenbaum; Alexandru Nicolau; Zhangxiaowen Gong (LCPC, 2017)

An empirical study of the effect of source-level loop transformations on compiler stability. - Zhangxiaowen Gong; Zhi Chen 001; Justin Josef Szaday; David C. Wong 001; Zehra Sura; Neftali Watkinson; Saeed Maleki; David A. Padua; Alexander V. Veidenbaum; Alexandru Nicolau; Josep Torrellas (Proc. ACM Program. Lang., 2018)

SparseTrain: Leveraging Dynamic Sparsity in Training DNNs on General-Purpose SIMD Processors. - Zhangxiaowen Gong; Houxiang Ji; Christopher W. Fletcher; Christopher J. Hughes; Josep Torrellas (CoRR, 2019)

SparseTrain: Leveraging Dynamic Sparsity in Software for Training DNNs on General-Purpose SIMD Processors. - Zhangxiaowen Gong; Houxiang Ji; Christopher W. Fletcher; Christopher J. Hughes; Josep Torrellas (PACT, 2020)

SAVE: Sparsity-Aware Vector Engine for Accelerating DNN Training and Inference on CPUs. - Zhangxiaowen Gong; Houxiang Ji; Christopher W. Fletcher; Christopher J. Hughes; Sara S. Baghsorkhi; Josep Torrellas (MICRO, 2020)

Graphite: optimizing graph neural networks on CPUs through cooperative software-hardware techniques. - Zhangxiaowen Gong; Houxiang Ji; Yao Yao; Christopher W. Fletcher; Christopher J. Hughes; Josep Torrellas (ISCA, 2022)