A novel 2.4-to-3.6 GHz wideband subharmonically injection-locked PLL with adaptively-aligned injection timing. - Zhao Zhang 004; Liyuan Liu; Nanjian Wu (A-SSCC, 2014)

A 1-V 5.2-5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS. - Jincheng Yang; Zhao Zhang 004; Peng Feng 001; Liyuan Liu; Nanjian Wu (ASICON, 2015)

A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Peng Feng 001; Jian Liu 021; Nanjian Wu (A-SSCC, 2017)

Terahertz detector for imaging in 180-nm standard CMOS process. - Zhao-yang Liu; Liyuan Liu; Zhao Zhang 004; Jian Liu 021; Nanjian Wu (Sci. China Inf. Sci., 2017)

A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Peng Feng 001; Jian Liu 021; Nanjian Wu (IEICE Electron. Express, 2017)

A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique. - Zhao Zhang 004; Liyuan Liu; Peng Feng 001; Nanjian Wu (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Nan Qi; Peng Feng 001; Jian Liu 021; Nanjian Wu (A-SSCC, 2018)

A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Peng Feng 001; Jian Liu 021; Nanjian Wu (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Low-Power Multiphase Clock Generator. - Zhao Zhang 004; Guang Zhu; Can Wang 009; Li Wang 083; C. Patrick Yue (A-SSCC, 2019)

A 0.65V 12-to-16GHz Sub-Sampling PLL with 56.4fsrms Integrated Jitter and -256.4dB FoM. - Zhao Zhang 004; Guang Zhu; C. Patrick Yue (ISSCC, 2019)

A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. - Can Wang 009; Guang Zhu; Zhao Zhang 004; C. Patrick Yue (VLSI Circuits, 2019)

A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz PLL Using an Offset Dual-Path Loop Architecture with Dynamic Charge Pumps. - Zhao Zhang 004; Guang Zhu; C. Patrick Yue (VLSI Circuits, 2019)

A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits. - Jincheng Yang; Zhao Zhang 004; Nan Qi; Liyuan Liu; Jian Liu 021; Nanjian Wu (Sci. China Inf. Sci., 2019)

Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors. - Qian Di; Zhongxing Zhang; Honglong Li; Zhao Zhang 004; Peng Feng 001; Nanjian Wu (IEICE Electron. Express, 2019)

0.1-5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Nan Qi; Peng Feng 001; Jian Liu 021; Nanjian Wu (IET Circuits Devices Syst., 2019)

An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique. - Zhao Zhang 004; Jincheng Yang; Liyuan Liu; Nan Qi; Peng Feng 001; Jian Liu 021; Nanjian Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator. - Zhao Zhang 004; Guang Zhu; Can Wang 009; Li Wang 083; C. Patrick Yue (IEEE J. Solid State Circuits, 2020)

A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fsrms Integrated Jitter and -256.4-dB FoM. - Zhao Zhang 004; Guang Zhu; C. Patrick Yue (IEEE J. Solid State Circuits, 2020)

A 15-Gb/s 0.0037-mm² 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator. - Junfeng Hu; Zhao Zhang 004; Quan Pan 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 50Gb/s High-Efficiency Si-Photonic Transmitter With Lump-Segmented MZM and Integrated PAM4 CDR. - Qiwen Liao; Miaofeng Li; Zhao Zhang 004; Jian Liu 021; Nanjian Wu; Xi Xiao; Nan Qi (CICC, 2021)

A 32×32 Array Terahertz Sensor in 65-nm CMOS Technology. - Tong Fang; Min Liu; Liyuan Liu; Ziteng Cai; Runjiang Dou; Peng Feng 001; Nan Qi; Zhao Zhang 004; Jian Liu 021; Nanjian Wu (ICTA, 2021)

A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM4 Receiver with a -8-dB JTRAN 40-MHz 0.2-UIPP JTOL Clock and Data Recovery. - Li Wang 083; Zhao Zhang 004; C. Patrick Yue (VLSI Circuits, 2021)

A 0.25-0.4-V, Sub-0.11-mW/GHz, 0.15-1.6-GHz PLL Using an Offset Dual-Path Architecture With Dynamic Charge Pumps. - Zhao Zhang 004; Guang Zhu; C. Patrick Yue (IEEE J. Solid State Circuits, 2021)

A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. - Can Wang 009; Li Wang 083; Zhao Zhang 004; Milad Kalantari Mahmoudabadi; Weimin Shi; C. Patrick Yue (IEEE Open J. Circuits Syst., 2021)

A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS. - Yihong Li; Sikai Chen; Yunqi Yang; Qianli Ma; Ming Zhong; Ziyi Lin; Leliang Li; Guike Li; Zhao Zhang 004; Liyuan Liu; Jian Liu 021; Nanjian Wu; et al. (APCCAS, 2022)

A 0.004-mm2 O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL. - Yixi Li; Xinyu Shen; Zhaoyu Zhang; Guike Li; Tao Yin; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu; Yong Chen 005; Zhao Zhang 004 (APCCAS, 2022)

A 0.006-mm26-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop. - Zhaoyu Zhang; Xinyu Shen; Yixi Li; Guike Li; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu; Yong Chen 005; Zhao Zhang 004 (APCCAS, 2022)

A 224-Gb/s Inverter-Based TIA with Interleaved Active-Feedback and Distributed Peaking in 28-nm CMOS for Silicon Photonic Receivers. - Sikai Chen; Jintao Xue; Leliang Li; Guike Li; Zhao Zhang 004; Jian Liu 021; Liyuan Liu; Binhao Wang; Yingtao Li; Nan Qi (ICTA, 2022)

A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR. - Qiwen Liao; Yuguang Zhang; Siyuan Ma; Lei Wang 187; Leliang Li; Guike Li; Zhao Zhang 004; Jian Liu 021; Nanjian Wu; Liyuan Liu; Yong Chen 005; Xi Xiao; et al. (IEEE J. Solid State Circuits, 2022)

Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects. - Jian He; Donglai Lu; Haiyun Xue; Sikai Chen; Han Liu; Leliang Li; Guike Li; Zhao Zhang 004; Jian Liu 021; Liyuan Liu; Nanjian Wu; Ningmei Yu; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS. - Jian He; Yuguang Zhang; Han Liu; Qiwen Liao; Zhao Zhang 004; Miaofeng Li; Fan Jiang; Jingbo Shi; Jian Liu 021; Nanjian Wu; Yong Chen 005; Patrick Yin Chiang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM. - Yixi Li; Zhao Zhang 004; Yong Chen 005; Xinyu Shen; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (A-SSCC, 2023)

A $ boldsymbol{4} times boldsymbol{112}- mathbf{Gb}/ mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics. - Han Liu; Nan Qi; Donglai Lu; Zizheng Dong; Zhihan Zhang; Jian He; Guike Li; Leliang Li; Ye Liu; Ziyue Dang; Daigao Chen; Zhao Zhang 004; et al. (A-SSCC, 2023)

A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6 GHz Bandwidth, $ boldsymbol{2.7} mathbf{pA}/ mathbf{Hz}^{ boldsymbol{0.5}}$ Input Referred Noise, and 103 $ mathbf{dB} mathbf{ Omega}$ Transimpedance Gain. - Yidan Zhang; Zhao Zhang 004; Yiqing Xu; Xinyu Shen; Nan Qi; Nanjian Wu; Jian Liu 021; Liyuan Liu (A-SSCC, 2023)

A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM. - Xinyu Shen; Zhao Zhang 004; Guike Li; Yong Chen 005; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (ESSCIRC, 2023)

A 0.0035-mm2 0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE. - Zhaoyu Zhang; Zhao Zhang 004; Yong Chen 005; Guoqing Wang; Xinyu Shen; Nan Qi; Guike Li; Shuangming Yu; Jian Liu 021; Nanjian Wu; Liyuan Liu (ESSCIRC, 2023)

A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process. - Guoqing Wang; Zhao Zhang 004; Xinyu Shen; Zhaoyu Zhang; Jian Liu 021; Nanjian Wu; Liyuan Liu (ICTA, 2023)

A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur. - Zhao Zhang 004; Xinyu Shen; Zhaoyu Zhang; Guike Li; Nan Qi; Jian Liu 021; Yong Chen 005; Nanjian Wu; Liyuan Liu (ISSCC, 2023)

A 64-Gb/s Reference-Less PAM4 CDR with Asymmetrical Linear Phase Detector Soring 231.5-fsrms Clock Jitter and 0.21-pJ/bit Energy Efficiency in 40-nm CMOS. - Zhao Zhang 004; Zhaoyu Zhang; Yong Chen 005; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (VLSI Technology and Circuits, 2023)

A 0.2-7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers. - Xiangyu Meng 003; Wang Xie; Jiaqi Zhang; Zhao Zhang 004 (IEEE Trans. Instrum. Meas., 2023)

A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O. - Sikai Chen; Mingyang You; Yunqi Yang; Ye Jin; Ziyi Lin; Yihong Li; Leliang Li; Guike Li; Yujun Xie; Zhao Zhang 004; Binhao Wang; Ningfeng Tang; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 19.58-to-21.38-GHz Low-Power Quad-Core VCO with Compact 3rd-Order Q-boost Inductors Achieving -191.8-dBc/Hz FoM and -205.4-dBc/Hz FoMA. - Xiangjian Kong; Shuai Deng; Zhao Zhang 004 (A-SSCC, 2024)

A 13.75-14.75-GHz 32.1-fsRMS Jitter -100.6-dBc Reference Spur -261.4-dB FoM Sub-Sampling PLL Using a KPD-Doubled Isolated Sub-Sampling Phase Detector for Reliable Spur-Jitter-Joint Optimization. - Yiqing Xu; Yixi Li; Zhao Zhang 004; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (A-SSCC, 2024)

A 64Gb/s Si-Photonic Micro-Ring Resonator Transceiver with Co-designed CMOS Driver and TIA for WDM Optical-IO. - Qianli Ma; Sikai Chen; Jintao Xue; Yingjie Ma; Yuean Gu; Chao Cheng; Yihan Chen; Haoran Yin; Guike Li; Zhao Zhang 004; Nanjian Wu; Ke Li; et al. (BCICTS, 2024)

A 0.144 mm212.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation. - Xinyu Shen; Zhao Zhang 004; Yong Chen 005; Yixi Li; Yidan Zhang; Guike Li; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (CICC, 2024)

A 32Gb/s NRZ Low-Bias DFB Driver with Frequency Boosting for High Efficiency Data Transmission. - Yang Min; Yi Zhang; Tao Yang; Leliang Li; Guike Li; Zhao Zhang 004; Jian Liu 021; Nanjian Wu; Yonghui Lin; Huiyao Peng; Jingbo Shi; Nan Qi (ISCAS, 2024)

A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR. - Li Wang 083; Zhao Zhang 004; Can Wang 009; Rehan Azmat; Weimin Shi; C. Patrick Yue (IEEE J. Solid State Circuits, 2024)

19.8 A 0.65V-VDD 10.4-to-11.8GHz Fractional-N Sampling PLL Achieving 73.8fsrms Jitter, -271.5dB FoMN, and -61 dBc in-Band Fractional Spur in 40nm CMOS. - Xinyu Shen; Zhao Zhang 004; Yixi Li; Junjie Chen; Xiangjian Kong; Nan Qi; Jian Liu 021; Nanjian Wu; Liyuan Liu (ISSCC, 2025)

A 6-64-Gb/s 0.41-pJ/Bit Reference-Less PAM4 CDR Using a Frequency-Detection-Gain-Enhanced PFD Achieving 19.8-Gb/s/μs Acquisition Speed. - Liyan Feng; Tuo Li; Xiaofeng Zou; Xiaoming Xiong; Zhao Zhang 004 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)