A memory-layout oriented run-time technique for locality optimization. - Yong Yan 003; Xiaodong Zhang 001; Zhao Zhang 010 (ICPP, 1998)

Cache-Optimal Methods for Bit-Reversals. - Zhao Zhang 010; Xiaodong Zhang 001 (SC, 1999)

A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. - Zhao Zhang 010; Zhichun Zhu; Xiaodong Zhang 001 (MICRO, 2000)

Cacheminer: A Runtime Approach to Exploit Cache Locality on SMP. - Yong Yan 003; Xiaodong Zhang 001; Zhao Zhang 010 (IEEE Trans. Parallel Distributed Syst., 2000)

Breaking Address Mapping Symmetry at Multi-levels of Memory Heirarchy to Reduce DRAM Row-buffer Conflicts. - Zhao Zhang 010; Zhichun Zhu; Xiaodong Zhang 001 (J. Instr. Level Parallelism, 2001)

Cached DRAM for ILP Processor Memory Access Latency Reduction. - Zhao Zhang 010; Zhichun Zhu; Xiaodong Zhang 001 (IEEE Micro, 2001)

Fast Bit-Reversals on Uniprocessors and Shared-Memory Multiprocessors. - Zhao Zhang 010; Xiaodong Zhang 001 (SIAM J. Sci. Comput., 2001)

Fine-Grain Priority Scheduling on Multi-Channel Memory Systems. - Zhichun Zhu; Zhao Zhang 010; Xiaodong Zhang 001 (HPCA, 2002)

An Efficient Anonymity Protocol for Grid Computing. - Souvik Ray; Zhao Zhang 010 (GRID, 2004)

Heuristic-Based Scheduling to Maximize Throughput of Data-Intensive Grid Applications. - Souvik Ray; Zhao Zhang 010 (IWDC, 2004)

Design and Optimization of Large Size and Low Overhead Off-Chip Caches. - Zhao Zhang 010; Zhichun Zhu; Xiaodong Zhang 001 (IEEE Trans. Computers, 2004)

A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. - Zhichun Zhu; Zhao Zhang 010 (HPCA, 2005)

Performance Characterization of Java Applications on SMT Processors. - Wei Huang 032; Jiang Lin; Zhao Zhang 010; J. Morris Chang (ISPASS, 2005)

Towards Pairing Java Applications on SMT Processors. - Wei Huang 032; Jiang Lin; Zhao Zhang 010; J. Morris Chang (MASCOTS, 2005)

Performance Modeling and Tuning Strategies of Mixed Mode Collective Communications. - Meng-Shiou Wu; Ricky A. Kendall; Kyle Wright; Zhao Zhang 010 (SC, 2005)

Component-oriented version management for hardware software co-design. - Tien N. Nguyen; Zhao Zhang 010 (CASCON, 2006)

Thermal modeling and management of DRAM memory systems. - Jiang Lin; Hongzhong Zheng; Zhichun Zhu; Howard David; Zhao Zhang 010 (ISCA, 2007)

DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. - Jiang Lin; Hongzhong Zheng; Zhichun Zhu; Zhao Zhang 010; Howard David (ISPASS, 2007)

Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems. - Jiang Lin; Qingda Lu; Xiaoning Ding; Zhao Zhang 010; Xiaodong Zhang 001; P. Sadayappan (HPCA, 2008)

Memory Access Scheduling Schemes for Systems with Multi-Core Processors. - Hongzhong Zheng; Jiang Lin; Zhao Zhang 010; Zhichun Zhu (ICPP, 2008)

BotTracer: Execution-Based Bot-Like Malware Detection. - Lei Liu 021; Songqing Chen; Guanhua Yan; Zhao Zhang 010 (ISC, 2008)

Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. - Hongzhong Zheng; Jiang Lin; Zhao Zhang 010; Eugene Gorbatov; Howard David; Zhichun Zhu (MICRO, 2008)

Software thermal management of dram memory for multicore systems. - Jiang Lin; Hongzhong Zheng; Zhichun Zhu; Eugene Gorbatov; Howard David; Zhao Zhang 010 (SIGMETRICS, 2008)

Reflections on Teaching and Learning in an Advanced Undergraduate Course in Embedded Systems. - Diane T. Rover; Ramon Mercado; Zhao Zhang 010; Mack C. Shelley; Daniel S. Helvick (IEEE Trans. Educ., 2008)

Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning. - Qingda Lu; Jiang Lin; Xiaoning Ding; Zhao Zhang 010; Xiaodong Zhang 001; P. Sadayappan (PACT, 2009)

Run-Time Detection of Malwares via Dynamic Control-Flow Inspection. - Yong-Joon Park; Zhao Zhang 010; Songqing Chen (ASAP, 2009)

Electronic Structure Calculations and Adaptation Scheme in Multi-core Computing Environments. - Lakshminarasimhan Seshagiri; Masha Sosonkina; Zhao Zhang 010 (ICCS (1), 2009)

Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. - Hongzhong Zheng; Jiang Lin; Zhao Zhang 010; Zhichun Zhu (ISCA, 2009)

Enabling software management for multicore caches with a lightweight hardware support. - Jiang Lin; Qingda Lu; Xiaoning Ding; Zhao Zhang 010; Xiaodong Zhang 001; P. Sadayappan (SC, 2009)

Exploring Tuning Strategies for Quantum Chemistry Computations. - Lakshminarasimhan Seshagiri; Meng-Shiou Wu; Masha Sosonkina; Zhao Zhang 010 (Software Automatic Tuning, From Concepts to State-of-the-Art Results, 2010)

Enhancing adaptive middleware for quantum chemistry applications with a database framework. - Lakshminarasimhan Seshagiri; Meng-Shiou Wu; Masha Sosonkina; Zhao Zhang 010; Mark S. Gordon; Michael W. Schmidt (IPDPS Workshops, 2010)

An Application-Level Data Transparent Authentication Scheme without Communication Overhead. - Songqing Chen; Shiping Chen 003; Xinyuan Wang 005; Zhao Zhang 010; Sushil Jajodia (IEEE Trans. Computers, 2010)

Memory Architecture for Integrating Emerging Memory Technologies. - Kun Fang 005; Long Chen; Zhao Zhang 010; Zhichun Zhu (PACT, 2011)

Palette: A Cache Leakage Energy Saving Technique for Green Computing. - Sparsh Mittal; Zhao Zhang 010 (High Performance Computing Workshop (2), 2012)

Free ECC: An efficient error protection for compressed last-level caches. - Long Chen; Yanan Cao 002; Zhao Zhang 010 (ICCD, 2013)

FlexiWay: A cache energy saving technique using fine-grained cache reconfiguration. - Sparsh Mittal; Zhao Zhang 010; Jeffrey S. Vetter (ICCD, 2013)

CASHIER: A Cache Energy Saving Technique for QoS Systems. - Sparsh Mittal; Zhao Zhang 010; Yanan Cao 002 (VLSI Design, 2013)

Achieving energy efficiency during collective communications. - Vaibhav Sundriyal; Masha Sosonkina; Zhao Zhang 010 (Concurr. Comput. Pract. Exp., 2013)

Energy saving strategies for parallel applications with point-to-point communication phases. - Vaibhav Sundriyal; Masha Sosonkina; Alexander Gaenko; Zhao Zhang 010 (J. Parallel Distributed Comput., 2013)

E3CC: A memory error protection scheme with novel address mapping for subranked and low-power memories. - Long Chen; Yanan Cao 002; Zhao Zhang 010 (ACM Trans. Archit. Code Optim., 2013)

Thermal Modeling and Management of DRAM Systems. - Jiang Lin; Hongzhong Zheng; Zhichun Zhu; Zhao Zhang 010 (IEEE Trans. Computers, 2013)

MemGuard: A low cost and energy efficient design to support and enhance memory system reliability. - Long Chen; Zhao Zhang 010 (ISCA, 2014)

Encache: a Dynamic Profiling-Based Reconfiguration Technique for Improving Cache Energy Efficiency. - Sparsh Mittal; Zhao Zhang 010 (J. Circuits Syst. Comput., 2014)

A Host-Based Approach for Unknown Fast-Spreading Worm Detection and Containment. - Songqing Chen; Lei Liu 021; Xinyuan Wang 005; Xinwen Zhang; Zhao Zhang 010 (ACM Trans. Auton. Adapt. Syst., 2014)

Mini-Rank: A Power-EfficientDDRx DRAM Memory Architecture. - Kun Fang 005; Hongzhong Zheng; Jiang Lin; Zhao Zhang 010; Zhichun Zhu (IEEE Trans. Computers, 2014)

Secure, Efficient and Fine-Grained Data Access Control Mechanism for P2P Storage Cloud. - Heng He; Ruixuan Li 001; Xinhua Dong; Zhao Zhang 010 (IEEE Trans. Cloud Comput., 2014)

Automatic runtime frequency-scaling system for energy savings in parallel applications. - Vaibhav Sundriyal; Masha Sosonkina; Zhao Zhang 010 (J. Supercomput., 2014)

MASTER: A Multicore Cache Energy-Saving Technique Using Dynamic Cache Reconfiguration. - Sparsh Mittal; Yanan Cao 002; Zhao Zhang 010 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Memory design for selective error protection. - Yanan Cao 002; Long Chen; Zhao Zhang 010 (ICCD, 2015)

Flexible memory: A novel main memory architecture with block-level memory compression. - Yanan Cao 002; Long Chen; Zhao Zhang 010 (NAS, 2015)

Discreet-PARA: Rowhammer Defense with Low Cost and High Efficiency. - Yicheng Wang; Yang Liu 114; Peiyun Wu; Zhao Zhang 010 (ICCD, 2021)