Mixed-signal system verification by SystemC/SystemC-AMS and HSIM-VCS in near field communication tag design. - Zhaori Bi; Wei Li; Dian Zhou; Xuan Zeng 001; Sheng-Guo Wang (ASICON, 2013)

Analog circuit performance bound estimation based on extreme value theory. - Minghua Li; Zhaori Bi; Dian Zhou; Xuan Zeng 001 (MWSCAS, 2015)

Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework. - Liuxi Qian; Zhaori Bi; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Optimization and Quality Estimation of Circuit Design via Random Region Covering Method. - Zhaori Bi; Dian Zhou; Sheng-Guo Wang; Xuan Zeng 001 (ACM Trans. Design Autom. Electr. Syst., 2017)

Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis. - Yishi Yang; Hengliang Zhu; Zhaori Bi; Changhao Yan; Dian Zhou; Yangfeng Su; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench. - Jingyao Zhao; Changhao Yan; Zhaori Bi; Fan Yang 001; Xuan Zeng 001; Dian Zhou (ASP-DAC, 2022)

A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion. - Xu Fu; Changhao Yan; Zhaori Bi; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ISCAS, 2022)

Learning From Highly Confident Samples for Automatic Knee Osteoarthritis Severity Assessment: Data From the Osteoarthritis Initiative. - Yifan Wang; Zhaori Bi; Yuxue Xie; Tao Wu; Xuan Zeng 001; Shuang Chen; Dian Zhou (IEEE J. Biomed. Health Informatics, 2022)

cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis. - Aidong Zhao; Xianan Wang; Zixiao Lin; Zhaori Bi; Xudong Li; Changhao Yan; Fan Yang 001; Li Shang; Dian Zhou; Xuan Zeng 001 (DAC, 2023)

A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling. - Biao He; Shuhan Zhang; Yifan Wang; Tianning Gao; Fan Yang 001; Changhao Yan; Dian Zhou; Zhaori Bi; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper). - Ruiyu Lyu; Yuan Meng; Aidong Zhao; Zhaori Bi; Keren Zhu 001; Fan Yang 001; Changhao Yan; Dian Zhou; Xuan Zeng 001 (ASPDAC, 2024)

Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing. - Xuyang Zhao; Zhaori Bi; Changhao Yan; Fan Yang 001; Ye Lu 005; Dian Zhou; Xuan Zeng 001 (ASPDAC, 2024)

HiMOSS: A Novel High-dimensional Multi-objective Optimization Method via Adaptive Gradient-Based Subspace Sampling for Analog Circuit Sizing. - Tianchen Gu; Ruiyu Lyu; Zhaori Bi; Changhao Yan; Fan Yang 001; Dian Zhou; Tao Cui; Xin Liu 001; Zaikun Zhang; Xuan Zeng 001 (DAC, 2024)

EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration. - Handa Sun; Zhaori Bi; Wenning Jiang; Ye Lu 005; Changhao Yan; Fan Yang 001; Wenchuang Hu; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (DAC, 2024)

tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling. - Tianchen Gu; Jiaqi Wang; Zhaori Bi; Changhao Yan; Fan Yang 001; Yajie Qin; Tao Cui; Xuan Zeng 001 (DATE, 2024)

Circuits Physics Constrained Predictor of Static IR Drop with Limited Data. - Yuan Meng; Ruiyu Lyu; Zhaori Bi; Changhao Yan; Fan Yang 001; Wenchuang Hu; Dian Zhou; Xuan Zeng 001 (DATE, 2024)

AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis. - Jintao Li; Haochang Zhi; Ruiyu Lyu; Wangzhen Li; Zhaori Bi; Keren Zhu 001; Yanhan Zeng; Weiwei Shan; Changhao Yan; Fan Yang 001; Yun Li 002; Xuan Zeng 001 (ICCAD, 2024)

Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis. - Ruiyu Lyu; Aidong Zhao; Yuan Meng; Keren Zhu 001; Zhaori Bi; Changhao Yan; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (ICCAD, 2024)

Exploring High-dimensional Search Space via Voronoi Graph Traversing. - Aidong Zhao; Xuyang Zhao; Tianchen Gu; Zhaori Bi; Xinwei Sun 001; Changhao Yan; Fan Yang 001; Dian Zhou; Xuan Zeng 001 (UAI, 2024)

pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment. - Zhaoting Chen; Junzhe Cai; Changhao Yan; Zhaori Bi; Yuzhe Ma; Bei Yu 001; Wenchuang Walter Hu; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis. - Tianchen Gu; Wangzhen Li; Aidong Zhao; Zhaori Bi; Xudong Li; Fan Yang 001; Changhao Yan; Wenchuang Walter Hu; Dian Zhou; Tao Cui; Xin Liu 001; Zaikun Zhang; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

D3PBO: Dynamic Domain Decomposition-based Parallel Bayesian Optimization for Large-scale Analog Circuit Sizing. - Aidong Zhao; Tianchen Gu; Zhaori Bi; Fan Yang 001; Changhao Yan; Xuan Zeng 001; Zixiao Lin; Wenchuang Walter Hu; Dian Zhou (ACM Trans. Design Autom. Electr. Syst., 2024)

ROI-HIT: Region of Interest-Driven High-Dimensional Microarchitecture Design Space Exploration. - Xuyang Zhao; Tianning Gao; Aidong Zhao; Zhaori Bi; Changhao Yan; Fan Yang 001; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Multiagent Based Reinforcement Learning (MA-RL): An Automated Designer for Complex Analog Circuits. - Jiarui Bao; Jinxin Zhang; Zhangcheng Huang 001; Zhaori Bi; Xingwei Feng; Xuan Zeng 001; Ye Lu 005 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

INTO-OA: Interpretable Topology Optimization for Operational Amplifiers. - Jinyi Shen; Fan Yang 001; Li Shang; Zhaori Bi; Changhao Yan; Dian Zhou; Xuan Zeng 001 (DATE, 2025)

An RISC-V PPA-Fusion Cooperative Optimization Framework Based on Hybrid Strategies. - Tianning Gao; Yifan Wang; Ming Zhu 016; Xiulong Wu; Dian Zhou; Zhaori Bi (IEEE Trans. Very Large Scale Integr. Syst., 2025)

ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers. - Jinyi Shen; Fan Yang 001; Li Shang; Changhao Yan; Zhaori Bi; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

VTSMOC: An Efficient Voronoi Tree Search Boosted Multiobjective Bayesian Optimization With Constraints for High-Dimensional Analog Circuit Synthesis. - Aidong Zhao; Ruiyu Lyu; Xuyang Zhao; Zhaori Bi; Fan Yang 001; Changhao Yan; Dian Zhou; Yangfeng Su; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

pPIRW: An Efficient and Accurate Precalculation Path Integral Random Walk Solver for Steady-State Thermal Simulation With Robin Boundary Conditions. - Zhixuan Dong; Longlong Yang; Cuiyang Ding; Changhao Yan; Zhaori Bi; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Hierarchical Integration of Reinforcement Learning and Optimization Algorithms for Time-Efficient Design Automation of Complex Analog Circuit. - Xingwei Feng; Yifan Xu; Zhangcheng Huang 001; Wuyi Xu; Zhaori Bi; Fan Yang 001; Xuan Zeng 001; Ye Lu 005 (ACM Trans. Design Autom. Electr. Syst., 2025)

APPLE-DSE: Asynchronous Parallel Pareto Set Learning for Microarchitecture Design Space Exploration. - Xuyang Zhao; Tianning Gao; Zheng Wu; Zhaori Bi; Changhao Yan; Fan Yang 001; Sheng-Guo Wang; Dian Zhou; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)