A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model. - Zhongyuan Feng; Bo Wang 023; Zhaoyang Zhang 008; An Guo 001; Xin Si (APCCAS, 2022)

A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks. - Bo Wang 023; Chen Xue; Zhongyuan Feng; Zhaoyang Zhang 008; Han Liu; Lizheng Ren; Xiang Li 147; Anran Yin; Tianzhu Xiong; Yeyang Xue; Shengnan He; Yuyao Kong; et al. (ISSCC, 2023)

From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits. - Zhaoyang Zhang 008; Jinwu Chen; Xi Chen 107; An Guo 001; Bo Wang 023; Tianzhu Xiong; Yuyao Kong; Xingyu Pu; Shengnan He; Xin Si; Jun Yang 006 (Sci. China Inf. Sci., 2023)

A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. - Zhaoyang Zhang 008; Zhichao Liu; Feiran Liu; Yinhai Gao; Yuchen Ma; Yutong Zhang; An Guo 001; Tianzhu Xiong; Jinwu Chen; Xi Chen 107; Bo Wang 023; Yuchen Tang; et al. (CICC, 2024)

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs. - An Guo 001; Xi Chen 107; Fangyuan Dong; Jinwu Chen; Zhihang Yuan; Xing Hu 010; Yuanpeng Zhang 002; Jingmin Zhang; Yuchen Tang; Zhican Zhang; Gang Chen 023; Dawei Yang; et al. (ISSCC, 2024)

ChipExpert: The Open-Source Integrated-Circuit-Design-Specific Large Language Model. - Ning Xu 009; Zhaoyang Zhang 008; Lei Qi 001; Wensuo Wang; Chao Zhang 005; Zihao Ren; Huaiyuan Zhang; Xin Cheng; Yanqi Zhang; Zhichao Liu; Qingwen Wei; Shiyang Wu; et al. (CoRR, 2024)

Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture. - Xi Chen 107; Yitong Zhao; An Guo 001; Jinwu Chen; Fangyuan Dong; Zhaoyang Zhang 008; Tianzhu Xiong; Bo Wang 023; Yuyao Kong; Xin Si (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer. - Xi Chen 107; Shaochen Li; Zhican Zhang; Wentao Zheng; Xiao Tan 001; Yuchen Tang; Yuhui Shi; Lizheng Ren; Yibo Mai; Feiran Liu; Jinwu Chen; Zhaoyang Zhang 008; et al. (ISSCC, 2025)

14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching. - An Guo 001; Jingmin Zhang; Xingyu Pu; Yi Yang 001; Defa Wu; Yuchen Tang; Yuhui Shi; Yinghai Gao; Zhichao Liu; Bo Wang 023; Tianzhu Xiong; Zhaoyang Zhang 008; et al. (ISSCC, 2025)

GCNIM: A Booth-6T-SRAM Based Graph-Convolutional-Networks-in-Memory Computing Macro. - Yan Yan 030; Zhaoyang Zhang 008; Shaochen Li; Defa Wu; Jun Yang 006; Xin Si (MCSoC, 2025)

Expansion of the memory pyramid in the era of large models: compute-intensive compute-in-memory and memory-intensive compute-in-memory. - Zhichao Liu; Yanqi Zhang; Zhican Zhang; Yi Yang 001; Zhaoyang Zhang 008; Xing Wang; Jinwu Chen; Xiaomin Li; Xin Si; Jun Yang 006 (Sci. China Inf. Sci., 2025)

A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs. - Zhaoyang Zhang 008; Yanqi Zhang; Feiran Liu; Zhichao Liu; Yinhai Gao; Yuchen Ma; Yutong Zhang; An Guo 001; Tianzhu Xiong; Jinwu Chen; Xi Chen 107; Bo Wang 023; et al. (IEEE J. Solid State Circuits, 2025)