An FPGA Accelerator With Efficient Weight Compression by Combining Bit-Level Sparsity and Mixed-Precision Quantization. - Yuanmiao Lin; Zhaozhang Feng; Xueming Li 001; Hongmin Huang; Ruidian Zhan; Xianghong Hu 001; Shuting Cai; Xiaoming Xiong (IEEE Trans. Circuits Syst. II Express Briefs, 2025)