An-OARSMan: obstacle-avoiding routing tree construction with good length performance. - Yu Hu 002; Tong Jing; Xianlong Hong; Zhe Feng 002; Xiaodong Hu 001; Guiying Yan (ASP-DAC, 2005)

CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model. - Yiyu Shi 001; Tong Jing; Lei He 001; Zhe Feng 002; Xianlong Hong (ASP-DAC, 2006)

An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. - Zhe Feng 002; Yu Hu 002; Tong Jing; Xianlong Hong; Xiaodong Hu 001; Guiying Yan (ISPD, 2006)

ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm. - Yu Hu 002; Tong Jing; Zhe Feng 002; Xianlong Hong; Xiaodong Hu 001; Guiying Yan (J. Comput. Sci. Technol., 2006)

lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity. - Tom Tong Jing; Zhe Feng 002; Yu Hu 002; Xianlong Hong; Xiaodong Hu 001; Guiying Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Robust FPGA resynthesis based on fault-tolerant Boolean matching. - Yu Hu 002; Zhe Feng 002; Lei He 001; Rupak Majumdar (ICCAD, 2008)

A full-scale solution to the rectilinear obstacle-avoiding Steiner problem. - Tom Tong Jing; Yu Hu 002; Zhe Feng 002; Xianlong Hong; Xiaodong Hu 001; Guiying Yan (Integr., 2008)

Fashion: A Fast and Accurate Solution to Global Routing Problem. - Zhen Cao; Tong Jing; Jinjun Xiong; Yu Hu 002; Zhe Feng 002; Lei He 001; Xianlong Hong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

IPR: In-Place Reconfiguration for FPGA fault tolerance. - Zhe Feng 002; Yu Hu 002; Lei He 001; Rupak Majumdar (ICCAD, 2009)

In-place decomposition for robustness in FPGA. - Ju-Yueh Lee; Zhe Feng 002; Lei He 001 (ICCAD, 2010)

Acceleration of Multi-agent Simulation on FPGAs. - Lintao Cui; Jing Chen; Yu Hu 002; Jinjun Xiong; Zhe Feng 002; Lei He 001 (FPL, 2011)

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs. - Zhe Feng 002; Naifeng Jing; GengSheng Chen; Yu Hu 002; Lei He 001 (FPL, 2011)

Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. - Naifeng Jing; Ju-Yueh Lee; Zhe Feng 002; Weifeng He; Zhigang Mao; Shi-Jie Wen; Rick Wong; Lei He 001 (FPL, 2011)

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. - Naifeng Jing; Ju-Yueh Lee; Zhe Feng 002; Weifeng He; Zhigang Mao; Lei He 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs. - Zhe Feng 002; Naifeng Jing; Lei He 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)