GPIOCP: Timing-accurate general purpose I/O controller for many-core real-time systems. - Zhe Jiang 004; Neil C. Audsley (DATE, 2017)

VCDC: The Virtualized Complicated Device Controller. - Zhe Jiang 004; Neil C. Audsley (ECRTS, 2017)

BlueVisor: A Scalable Real-Time Hardware Hypervisor for Many-Core Embedded Systems. - Zhe Jiang 004; Neil C. Audsley; Pan Dong (RTAS, 2018)

TZDKS: A New TrustZone-Based Dual-Criticality System with Balanced Performance. - Pan Dong; Alan Burns 001; Zhe Jiang 004; Xiangke Liao (RTCSA, 2018)

Real-time I/O system for many-core embedded systems. - Zhe Jiang 004 (2018)

MCS-IOV: Real-Time I/O Virtualization for Mixed-Criticality Systems. - Zhe Jiang 004; Neil C. Audsley; Pan Dong; Nan Guan; Xiaotian Dai 001; Lifeng Wei (RTSS, 2019)

Work-in-Progress: Real-Time RPC for Hybrid Dual-OS System. - Pan Dong; Zhe Jiang 004; Alan Burns 001; Yan Ding; Jun Ma 015 (RTSS, 2019)

BlueIO: A Scalable Real-Time Hardware I/O Virtualization System for Many-core Embedded Systems. - Zhe Jiang 004; Neil C. Audsley; Pan Dong (ACM Trans. Embed. Comput. Syst., 2019)

Timing-Accurate General-Purpose I/O for Multi- and Many-Core Systems: Scheduling and Hardware Support. - Shuai Zhao 004; Zhe Jiang 004; Xiaotian Dai 001; Iain Bate; Ibrahim Habli; Wanli Chang 001 (DAC, 2020)

All In One Network for Driver Attention Monitoring. - Dawei Yang; Xinlei Li; Xiaotian Dai 001; Rui Zhang; Lizhe Qi; Wenqiang Zhang; Zhe Jiang 004 (ICASSP, 2020)

Re-Thinking Mixed-Criticality Architecture for Automotive Industry. - Zhe Jiang 004; Shuai Zhao 004; Pan Dong; Dawei Yang; Ran Wei; Nan Guan; Neil C. Audsley (ICCD, 2020)

Pythia-MCS: Enabling Quarter-Clairvoyance in I/O-Driven Mixed-Criticality Systems. - Zhe Jiang 004; Kecheng Yang 001; Nathan Fisher; Neil C. Audsley; Zheng Dong 002 (RTSS, 2020)

Build real-time communication for hybrid dual-OS system. - Pan Dong; Zhe Jiang 004; Alan Burns 001; Yan Ding; Jun Ma 015 (J. Syst. Archit., 2020)

I/O-GUARD: Hardware/Software Co-Design for I/O Virtualization with Guaranteed Real-time Performance. - Zhe Jiang 004; Kecheng Yang 001; Yunfeng Ma; Nathan Fisher; Neil C. Audsley; Zheng Dong 002 (DAC, 2021)

Adaptable Ensemble Distillation. - Yankai Wang; Dawei Yang; Wei Zhang 056; Zhe Jiang 004; Wenqiang Zhang (ICASSP, 2021)

Brief Industry Paper: AXI-InterconnectRT: Towards a Real-Time AXI-Interconnect for System-on-Chips. - Zhe Jiang 004; Neil C. Audsley; Dayu Shill; Kecheng Yang 001; Nathan Fisher; Zheng Dong 002 (RTAS, 2021)

Work-in-Progress: a static partition for shared cache in mixed-time-sensitive system with balanced performance. - Pan Yang 021; Pan Dong; Zhe Jiang 004; Jintao Xia; Yan Ding (RTCSA, 2021)

HIART-MCS: High Resilience and Approximated Computing Architecture for Imprecise Mixed-Criticality Systems. - Zhe Jiang 004; Xiaotian Dai 001; Neil C. Audsley (RTSS, 2021)

BlueScale: a scalable memory architecture for predictable real-time computing on highly integrated SoCs. - Zhe Jiang 004; Kecheng Yang 001; Neil C. Audsley; Nathan Fisher; Weisong Shi; Zheng Dong 002 (DAC, 2022)

Designing critical systems with iterative automated safety analysis. - Ran Wei; Zhe Jiang 004; Xiaoran Guo; Haitao Mei; Athanasios Zolotas; Tim Kelly (DAC, 2022)

PSpSys: A time-predictable mixed-criticality system architecture based on ARM TrustZone. - Zhe Jiang 004; Pan Dong; Ran Wei; Qingling Zhao; Yankai Wang; Dizhong Zhu; Yan Zhuang; Neil C. Audsley (J. Syst. Archit., 2022)

Towards an energy-efficient quarter-clairvoyant mixed-criticality system. - Zhe Jiang 004; Kecheng Yang 001; Nathan Fisher; Neil C. Audsley; Zheng Dong 002 (J. Syst. Archit., 2022)

Schedulability analysis and stack size minimization for adaptive mixed criticality scheduling with semi-Clairvoyance and preemption thresholds. - Qingling Zhao; Mengfei Qu; Bo Huang; Zhe Jiang 004; Haibo Zeng 001 (J. Syst. Archit., 2022)

BlueVisor: Time-Predictable Hardware Hypervisor for Many-Core Embedded Systems. - Zhe Jiang 004; Ran Wei; Pan Dong; Yan Zhuang; Neil C. Audsley; Ian Gray (IEEE Trans. Computers, 2022)

Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems. - Zhe Jiang 004; Xiaotian Dai 001; Pan Dong; Ran Wei; Dawei Yang; Neil C. Audsley; Nan Guan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Bridging the Pragmatic Gaps for Mixed-Criticality Systems in the Automotive Industry. - Zhe Jiang 004; Shuai Zhao 004; Ran Wei; Dawei Yang; Richard Paterson; Nan Guan; Yan Zhuang; Neil C. Audsley (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Many-Core Real-Time Network-on-Chip I/O Systems for Reducing Contention and Enhancing Predictability. - Zhe Jiang 004; Xiaotian Dai 001; Shuai Zhao 004; Ran Wei; Ian Gray (CPS-IoT Week Workshops, 2023)

BlueFace: Integrating an Accelerator into the Core's Pipeline through Algorithm-Interface Co-Design for Real-Time SoCs. - Zhe Jiang 004; Nathan Fisher; Nan Guan; Zheng Dong 002 (DAC, 2023)

A High-Resilience Imprecise Computing Architecture for Mixed-Criticality Systems. - Zhe Jiang 004; Xiaotian Dai 001; Alan Burns 001; Neil C. Audsley; Zonghua Gu 001; Ian Gray (IEEE Trans. Computers, 2023)

Towards Hard Real-Time and Energy-Efficient Virtualization for Many-Core Embedded Systems. - Zhe Jiang 004; Kecheng Yang 001; Yunfeng Ma; Nathan Fisher; Neil C. Audsley; Zheng Dong 002 (IEEE Trans. Computers, 2023)

AXI-IC$^{ mathrm{ RT}}$ RT : Towards a Real-Time AXI-Interconnect for Highly Integrated SoCs. - Zhe Jiang 004; Kecheng Yang 001; Nathan Fisher; Ian Gray; Neil C. Audsley; Zheng Dong 002 (IEEE Trans. Computers, 2023)

NPRC-I/O: An NoC-Based Real-Time I/O System With Reduced Contention and Enhanced Predictability. - Zhe Jiang 004; Xiaotian Dai 001; Ran Wei; Ian Gray; Zonghua Gu 001; Qingling Zhao; Shuai Zhao 004 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Make Each Iteration Count. - Yuchen Hu; Ke Xu; Jialin Sun; Xinwei Fang; Weiwei Shan; Xi Wang 009; Zhe Jiang 004 (ACM TUR-C, 2024)

A Cache/Algorithm Co-design for Parallel Real-Time Systems with Data Dependency on Multi/Many-core System-on-Chips. - Zhe Jiang 004; Shuai Zhao 004; Ran Wei; Yiyang Gao; Jing Li 025 (DAC, 2024)

MEIC: Re-thinking RTL Debug Automation using LLMs. - Ke Xu; Jialin Sun; Yuchen Hu; Xinwei Fang; Weiwei Shan; Xi Wang 009; Zhe Jiang 004 (ICCAD, 2024)

Optimization of NUMA Aware DNN Computing System. - Xiaoxiang Fang; Pan Dong; Jun Luo; Leilei Li; Yan Ding; Zhe Jiang 004 (ICIC (4), 2024)

Adaptive Optimisation of PyTorch Memory Pools for DNNs. - Leilei Li; Jun Luo; Pan Dong; Xiaoxiang Fang; Axin Yu; Zhe Jiang 004 (PRICAI (1), 2024)

ROTA-I/O: Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness. - Zhe Jiang 004; Shuai Zhao 004; Ran Wei; Xin Si; Gang Chen 023; Nan Guan (RTSS, 2024)

MESC: Re-thinking Algorithmic Priority and/or Criticality Inversions for Heterogeneous MCSs. - Jiapeng Guan; Ran Wei; Dean You; Yingquan Wang; Ruizhe Yang; Hui Wang; Zhe Jiang 004 (RTSS, 2024)

Large Language Model for Verilog Generation with Golden Code Feedback. - Ning Wang 071; Bingkun Yao; Jie Zhou; Xi Wang 009; Zhe Jiang 004; Nan Guan (CoRR, 2024)

Hardware/Algorithm Co-design for Real-Time I/O Control with Improved Timing Accuracy and Robustness. - Zhe Jiang 004; Shuai Zhao 004; Ran Wei; Xin Si; Gang Chen 023; Nan Guan (CoRR, 2024)

Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog. - Bingkun Yao; Ning Wang 071; Jie Zhou; Xi Wang 009; Hong Gao; Zhe Jiang 004; Nan Guan (CoRR, 2024)

UVLLM: An Automated Universal RTL Verification Framework using LLMs. - Yuchen Hu; Junhao Ye; Ke Xu; Jialin Sun; Shiyue Zhang; Xinyao Jiao; Dingrong Pan; Jie Zhou; Ning Wang 071; Weiwei Shan; Xinwei Fang; Xi Wang 009; et al. (CoRR, 2024)

Towards an extensible model-based digital twin framework for space launch vehicles. - Ran Wei; Ruizhe Yang; Shijun Liu; Chongsheng Fan; Rong Zhou; Zekun Wu 005; Haochi Wang; Yifan Cai; Zhe Jiang 004 (J. Ind. Inf. Integr., 2024)

On the degree of parallelism for parallel real-time tasks. - Qingqiang He; Nan Guan; Zhe Jiang 004; Mingsong Lv (J. Syst. Archit., 2024)

An efficient multi-task learning CNN for driver attention monitoring. - Dawei Yang; Yan Wang; Ran Wei; Jiapeng Guan; Xiaohua Huang; Wei Cai; Zhe Jiang 004 (J. Syst. Archit., 2024)

Automated Model-Based Assurance Case Management Using Constrained Natural Language. - Ran Wei; Zhe Jiang 004; Haitao Mei; Konstantinos Barmpis; Simon Foster 001; Tim Kelly; Yan Zhuang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Hopscotch: A Hardware-Software Co-Design for Efficient Cache Resizing on Multi-Core SoCs. - Zhe Jiang 004; Kecheng Yang 001; Nathan Fisher; Nan Guan; Neil C. Audsley; Zheng Dong 002 (IEEE Trans. Parallel Distributed Syst., 2024)

Post-training quantization for re-parameterization via coarse & fine weight splitting. - Dawei Yang; Ning He; Xing Hu 010; Zhihang Yuan; Jiangyong Yu; Chen Xu; Zhe Jiang 004 (J. Syst. Archit., 2024)

DECISIVE: Designing Critical Systems With Iterative Automated Safety Analysis. - Ran Wei; Zhe Jiang 004; Xiaoran Guo; Ruizhe Yang; Haitao Mei; Athanasios Zolotas; Tim Kelly (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Pushing the Limits of BFP on Narrow Precision LLM Inference. - Hui Wang; Yuan Cheng; Xiaomeng Han; Zhengpeng Zhao; Dawei Yang; Zhe Jiang 004 (AAAI, 2025)

OSTQuant: Refining Large Language Model Quantization with Orthogonal and Scaling Transformations for Better Distribution Fitting. - Xing Hu 010; Yuan Cheng; Dawei Yang; Zhixuan Chen; Zukang Xu; Jiangyong Yu; Chen Xu; Zhihang Yuan; Zhe Jiang 004; Sifan Zhou (ICLR, 2025)

OstQuant: Refining Large Language Model Quantization with Orthogonal and Scaling Transformations for Better Distribution Fitting. - Xing Hu 010; Yuan Cheng; Dawei Yang; Zukang Xu; Zhihang Yuan; Jiangyong Yu; Chen Xu; Zhe Jiang 004; Sifan Zhou (CoRR, 2025)

NVR: Vector Runahead on NPUs for Sparse Memory Access. - Hui Wang; Zhengpeng Zhao; Jing Wang; Yushu Du; Yuan Cheng; Bing Guo; He Xiao; Chenhao Ma 006; Xiaomeng Han; Dean You; Jiapeng Guan; Ran Wei; et al. (CoRR, 2025)

Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined Behaviors. - Renshuang Jiang; Pan Dong; Zhenling Duan; Yu Shi; Xiaoxiang Fang; Yan Ding; Jun Ma 015; Shuai Zhao 004; Zhe Jiang 004 (CoRR, 2025)

Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design. - Jie Zhou; Youshu Ji; Ning Wang 071; Yuchen Hu; Xinyao Jiao; Bingkun Yao; Xinwei Fang; Shuai Zhao 004; Nan Guan; Zhe Jiang 004 (CoRR, 2025)

MERE: Hardware-Software Co-Design for Masking Cache Miss Latency in Embedded Processors. - Dean You; Jieyu Jiang; Xiaoxuan Wang; Yushu Du; Zhihang Tan; Wenbo Xu; Hui Wang; Jiapeng Guan; Zhenyuan Wang; Ran Wei; Shuai Zhao 004; Zhe Jiang 004 (CoRR, 2025)

Exploiting the Uncertainty of the Longest Paths: Response Time Analysis for Probabilistic DAG Tasks. - Yiyang Gao; Shuai Zhao 004; Boyang Li; Xinwei Fang; Zhiyang Lin; Zhe Jiang 004; Nan Guan (CoRR, 2025)

Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback. - Ning Wang 071; Bingkun Yao; Jie Zhou; Yuchen Hu; Xi Wang 009; Nan Guan; Zhe Jiang 004 (CoRR, 2025)

VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction. - Ning Wang 071; Bingkun Yao; Jie Zhou; Yuchen Hu; Xi Wang 009; Nan Guan; Zhe Jiang 004 (CoRR, 2025)

From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification. - Junhao Ye; Yuchen Hu; Ke Xu; Dingrong Pan; Qichun Chen; Jie Zhou; Shuai Zhao 004; Xinwei Fang; Xi Wang 009; Nan Guan; Zhe Jiang 004 (CoRR, 2025)

ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection. - Juxin Niu; Xiangfeng Liu; Dan Niu; Xi Wang 009; Zhe Jiang 004; Nan Guan (CoRR, 2025)

FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification. - Gwok-Waa Wan; Shengchu Su; Ruihu Wang; Qixiang Chen; Sam-Zaak Wong; Mengnv Xing; Hefei Feng; Yubo Wang; Yinan Zhu; Jingyi Zhang; Jianmin Ye; Xinlai Wan; et al. (CoRR, 2025)

Thetis-lathe: Guidance on Reducing Residual Safety Obstacle in System Software from Rust Source Codes. - Renshuang Jiang; Pan Dong; Yan Ding; Ran Wei; Zhe Jiang 004 (ACM Trans. Embed. Comput. Syst., 2025)

Re-thinking Memory-Bound Limitations in CGRAs. - Xiangfeng Liu; Zhe Jiang 004; Anzhen Zhu; Xiaomeng Han; Mingsong Lyu; Qingxu Deng; Nan Guan (CoRR, 2025)