Decision tree based hardware power monitoring for run time dynamic power management in FPGA. - Zhe Lin 007; Wei Zhang 012; Sharad Sinha (FPL, 2017)

Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. - Zhe Lin 007; Sharad Sinha; Hao Liang 003; Liang Feng 001; Wei Zhang 012 (IEEE Trans. Multi Scale Comput. Syst., 2018)

Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA. - Zhe Lin 007; Sharad Sinha; Wei Zhang 012 (FCCM, 2019)

An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power. - Zhe Lin 007; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. - Zhe Lin 007; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (ASP-DAC, 2020)

PanGu-α: Large-scale Autoregressive Pretrained Chinese Language Models with Auto-parallel Computation. - Wei Zeng 006; Xiaozhe Ren; Teng Su; Hui Wang 030; Yi Liao; Zhiwei Wang; Xin Jiang 002; ZhenZhang Yang; Kaisheng Wang; Xiaoda Zhang; Chen Li 023; Ziyan Gong; et al. (CoRR, 2021)

Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System. - Zhe Lin 007; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs. - Zhe Lin 007; Zike Yuan; Jieru Zhao; Wei Zhang 012; Hui Wang 030; Yonghong Tian 001 (DATE, 2022)

MARS: Exploiting Multi-Level Parallelism for DNN Workloads on Adaptive Multi-Accelerator Systems. - Guan Shen; Jieru Zhao; Zeke Wang; Zhe Lin 007; Wenchao Ding 001; Chentao Wu; Quan Chen 002; Minyi Guo (DAC, 2023)

HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS. - Zhe Lin 007; Tingyuan Liang; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs. - Mingzhe Gao; Jieru Zhao; Zhe Lin 007; Minyi Guo (DATE, 2024)

GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network. - Chunyou Su; Linfeng Du; Tingyuan Liang; Zhe Lin 007; Maolin Wang 002; Sharad Sinha; Wei Zhang 012 (FPGA, 2024)

AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs. - Mingzhe Gao; Jieru Zhao; Zhe Lin 007; Wenchao Ding 001; Xiaofeng Hou; Yu Feng 007; Chao Li 009; Minyi Guo (ICCD, 2024)

Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator. - Jian Peng; Tingyuan Liang; Jingbo Jiang; Yipu Zhang; Zhe Lin 007; Zhiyao Xie; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms. - Enlai Li; Zhe Lin 007; Sharad Sinha; Wei Zhang 012 (FPGA, 2025)