Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories. - Xuan Wang 001; Jiang Xu 001; Wei Zhang 012; Xiaowen Wu; Yaoyao Ye; Zhehui Wang; Mahdi Nikdast; Zhe Wang 003 (DATE, 2013)

System-level analysis of mesh-based hybrid optical-electronic network-on-chip. - Yaoyao Ye; Xiaowen Wu; Jiang Xu 001; Mahdi Nikdast; Zhehui Wang; Xuan Wang 001; Zhe Wang 003 (ISCAS, 2013)

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip. - Yaoyao Ye; Jiang Xu 001; Baihan Huang; Xiaowen Wu; Wei Zhang 012; Xuan Wang 001; Mahdi Nikdast; Zhehui Wang; Weichen Liu; Zhe Wang 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

A systematic network-on-chip traffic modeling and generation methodology. - Zhe Wang 003; Weichen Liu; Jiang Xu 001; Xiaowen Wu; Zhehui Wang; Bin Li 018; Ravi R. Iyer 001; Ramesh Illikkal (APCCAS, 2014)

Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors. - Xuan Wang 001; Jiang Xu 001; Zhe Wang 003; Kevin J. Chen; Xiaowen Wu; Zhehui Wang (DATE, 2014)

A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs. - Zhe Wang 003; Weichen Liu; Jiang Xu 001; Bin Li 018; Ravi R. Iyer 001; Ramesh Illikkal; Xiaowen Wu; Wai Ho Mow; Wenjing Ye (ISVLSI, 2014)

Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors. - Zhehui Wang; Jiang Xu 001; Xiaowen Wu; Yaoyao Ye; Wei Zhang 012; Mahdi Nikdast; Xuan Wang 001; Zhe Wang 003 (IEEE Trans. Computers, 2014)

Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip. - Mahdi Nikdast; Jiang Xu 001; Xiaowen Wu; Wei Zhang 012; Yaoyao Ye; Xuan Wang 001; Zhehui Wang; Zhe Wang 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip. - Yaoyao Ye; Zhehui Wang; Peng Yang 003; Jiang Xu 001; Xiaowen Wu; Xuan Wang 001; Mahdi Nikdast; Zhe Wang 003; Luan H. K. Duong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Alleviate chip I/O pin constraints for multicore processors through optical interconnects. - Zhehui Wang; Jiang Xu 001; Peng Yang 003; Xuan Wang 001; Zhe Wang 003; Luan H. K. Duong; Zhifei Wang; Haoran Li 002; Rafael Kioji Vivas Maeda; Xiaowen Wu; Yaoyao Ye; Qinfen Hao (ASP-DAC, 2015)

Adaptively tolerate power-gating-induced power/ground noise under process variations. - Zhe Wang 003; Xuan Wang 001; Jiang Xu 001; Xiaowen Wu; Zhehui Wang; Peng Yang 003; Luan H. K. Duong; Haoran Li 002; Rafael Kioji Vivas Maeda; Zhifei Wang (DATE, 2015)

Memory Access Analysis of Many-core System with Abundant Bandwidth. - Chuan Tang; Dan Liu; Zuocheng Xing; Peng Yang 003; Zhe Wang 003; Jiang Xu 001 (MCSoC, 2015)

An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators. - Xuan Wang 001; Jiang Xu 001; Zhe Wang 003; Kevin J. Chen; Xiaowen Wu; Zhehui Wang; Peng Yang 003; Luan H. K. Duong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Fat-Tree-Based Optical Interconnection Networks Under Crosstalk Noise Constraint. - Mahdi Nikdast; Jiang Xu 001; Luan H. K. Duong; Xiaowen Wu; Zhehui Wang; Xuan Wang 001; Zhe Wang 003 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison. - Mahdi Nikdast; Jiang Xu 001; Luan Huu Kinh Duong; Xiaowen Wu; Xuan Wang 001; Zhehui Wang; Zhe Wang 003; Peng Yang 003; Yaoyao Ye; Qinfen Hao (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC. - Xuan Wang 001; Jiang Xu 001; Wei Zhang 012; Xiaowen Wu; Yaoyao Ye; Zhehui Wang; Mahdi Nikdast; Zhe Wang 003 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

An Inter/Intra-Chip Optical Network for Manycore Processors. - Xiaowen Wu; Jiang Xu 001; Yaoyao Ye; Xuan Wang 001; Mahdi Nikdast; Zhehui Wang; Zhe Wang 003 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models. - Rafael K. V. Maeda; Peng Yang 003; Xiaowen Wu; Zhe Wang 003; Jiang Xu 001; Zhehui Wang; Haoran Li 002; Luan H. K. Duong; Zhifei Wang (AISTECS@HiPEAC, 2016)

Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign. - Xuan Wang 001; Jiang Xu 001; Zhe Wang 003; Haoran Li 002; Peng Yang 003; Luan H. K. Duong; Rafael K. V. Maeda; Zhifei Wang (ACM J. Emerg. Technol. Comput. Syst., 2016)

Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks. - Luan H. K. Duong; Zhehui Wang; Mahdi Nikdast; Jiang Xu 001; Peng Yang 003; Zhifei Wang; Zhe Wang 003; Rafael K. V. Maeda; Haoran Li 002; Xuan Wang 001; Sébastien Le Beux; Yvain Thonnart (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC. - Zhe Wang 003; Xuan Wang 001; Jiang Xu 001; Haoran Li 002; Rafael K. V. Maeda; Zhehui Wang; Peng Yang 003; Luan H. K. Duong; Zhifei Wang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects. - Zhehui Wang; Jiang Xu 001; Peng Yang 003; Luan Huu Kinh Duong; Zhifei Wang; Xuan Wang 001; Zhe Wang 003; Haoran Li 002; Rafael Kioji Vivas Maeda (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Improve Chip Pin Performance Using Optical Interconnects. - Zhehui Wang; Jiang Xu 001; Peng Yang 003; Xuan Wang 001; Zhe Wang 003; Luan Huu Kinh Duong; Zhifei Wang; Rafael Kioji Vivas Maeda; Haoran Li 002 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Modular reinforcement learning for self-adaptive energy efficiency optimization in multicore system. - Zhe Wang 003; Zhongyuan Tian; Jiang Xu 001; Rafael K. V. Maeda; Haoran Li 002; Peng Yang 003; Zhehui Wang; Luan H. K. Duong; Zhifei Wang; Xuanqi Chen (ASP-DAC, 2017)

MOCA: an Inter/Intra-Chip Optical Network for Memory. - Zhehui Wang; Zhengbin Pang; Peng Yang 003; Jiang Xu 001; Xuanqi Chen; Rafael K. V. Maeda; Zhifei Wang; Luan H. K. Duong; Haoran Li 002; Zhe Wang 003 (DAC, 2017)

Adaptive power delivery system management for many-core processors with on/off-chip voltage regulators. - Haoran Li 002; Jiang Xu 001; Zhe Wang 003; Peng Yang 003; Rafael K. V. Maeda; Zhongyuan Tian (DATE, 2017)

Fast and Accurate Exploration of Multi-level Caches Using Hierarchical Reuse Distance. - Rafael K. V. Maeda; Qiong Cai; Jiang Xu 001; Zhe Wang 003; Zhongyuan Tian (HPCA, 2017)

Energy-Efficient Power Delivery System Paradigms for Many-Core Processors. - Haoran Li 002; Xuan Wang 001; Jiang Xu 001; Zhe Wang 003; Rafael K. V. Maeda; Zhehui Wang; Peng Yang 003; Luan H. K. Duong; Zhifei Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Multi-device collaborative management through knowledge sharing. - Zhongyuan Tian; Zhe Wang 003; Haoran Li 002; Peng Yang 003; Rafael Kioji Vivas Maeda; Jiang Xu 001 (ASP-DAC, 2018)

Workload-Aware Adaptive Power Delivery System Management for Many-Core Processors. - Haoran Li 002; Jiang Xu 001; Zhe Wang 003; Rafael K. V. Maeda; Peng Yang 003; Zhongyuan Tian (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems. - Weichen Liu; Zhe Wang 003; Peng Yang 003; Jiang Xu 001; Bin Li 018; Ravi R. Iyer 001; Ramesh Illikkal (IEEE Trans. Multi Scale Comput. Syst., 2018)

Collaborative Power Management Through Knowledge Sharing Among Multiple Devices. - Zhongyuan Tian; Zhe Wang 003; Jiang Xu 001; Haoran Li 002; Peng Yang 003; Rafael Kioji Vivas Maeda (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)