An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays. - Zhen-guo Ma; Feng Yu 003; Rui-feng Ge; Ze-ke Wang (J. Zhejiang Univ. Sci. C, 2011)

A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm. - Zhen-guo Ma; Xiaobo Yin; Feng Yu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Time Delay Estimation via Co-Prime Aliased Sparse FFT. - Bei Zhao; Chen Cheng; Zhen-guo Ma; Feng Yu 003 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Efficient Circuit for Parallel Bit Reversal. - Weijun Li 001; Feng Yu 003; Zhen-guo Ma (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths. - Xiaobo Yin; Feng Yu 003; Zhen-guo Ma (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A Novel Memory-Based Radix-2 Fast Walsh-Hadamard-Fourier Transform Architecture. - Qianjian Xing; Zhen-guo Ma; Feng Yu 003 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Continuous-Flow Memory-Based Architecture for Real-Valued FFT. - Xiubin Mao; Zhen-guo Ma; Feng Yu 003; Qianjian Xing (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Novel Conflict-Free Parallel Memory Access Scheme for FFT Processors. - Qianjian Xing; Zhen-guo Ma; Yingke Xu (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Fused Continuous Floating-Point MAC on FPGA. - Min Yuan; Qianjian Xing; Zhen-guo Ma; Feng Yu 003; Yingke Xu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Comparing Performance of Iterative and Non-Iterative Classifiers for 2-Lead ECGs on Multi-Feature Schemes. - Zhenguo Ma; Bingrui Chen; Yuan Xu; Yangxiao Li; Yatao Zhang (CISP-BMEI, 2019)

Pipelined Algorithm and Modular Architecture for Matrix Transposition. - Yunxiang Wang; Zhen-guo Ma; Feng Yu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Resource-Efficient Parallel Tree-Based Join Architecture on FPGA. - Huan Zhang 004; Bei Zhao; Wei-Jun Li 001; Zhen-Guo Ma; Feng Yu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Automatic Modulation Classification Based on Hierarchical Recurrent Neural Networks With Grouped Auxiliary Memory. - Ke Zang; Zhenguo Ma (IEEE Access, 2020)

Nonlinear Quality Indices Based on a Novel Lempel-Ziv Complexity for Assessing Quality of Multi-Lead ECGs Collected in Real Time. - Yatao Zhang; Zhenguo Ma; Wentao Dong (J. Inf. Process. Syst., 2020)

HKSiamFC: Visual-Tracking Framework Using Prior Information Provided by Staple and Kalman Filter. - Chenpu Li; Qianjian Xing; Zhenguo Ma (Sensors, 2020)

High-Throughput Parallel SRAM-Based Hash Join Architecture on FPGA. - Wen-Qi Wu; Meiting Xue; Tian-Qi Zhu; Zhen-Guo Ma; Feng Yu 003 (IEEE Trans. Circuits Syst., 2020)

FPGA-Accelerated Hash Join Operation for Relational Databases. - Meiting Xue; Qianjian Xing; Chen Feng; Feng Yu 003; Zhen-Guo Ma (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

MFCFSiam: A Correlation-Filter-Guided Siamese Network with Multifeature for Visual Tracking. - Chenpu Li; Qianjian Xing; Zhenguo Ma; Ke Zang (Wirel. Commun. Mob. Comput., 2020)

Joint Network Selection and Task Offloading in Mobile Edge Computing. - Xin Qi; Hongli Xu; Zhenguo Ma; Suo Chen (CCGRID, 2021)

Communication-efficient asynchronous federated learning in resource-constrained edge computing. - Jianchun Liu; Hongli Xu; Yang Xu 020; Zhenguo Ma; Zhiyuan Wang 002; Chen Qian 001; He Huang 001 (Comput. Networks, 2021)

A Novel Pipelined Algorithm and Modular Architecture for Non-Square Matrix Transposition. - Bo Zhang 097; Zhenguo Ma; Feng Yu 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Stream-Based Lossless Compression of Sensor Signals Using an Integer Adaptive Predictor. - Qianhao Chen; Wenqi Wu; Haori Zheng; Bei Zhao; Zhenguo Ma; Weijie Chen 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Pipelined Algorithm and Area-Efficient Architecture for Serial Real-Valued FFT. - Hongji Fang; Bo Zhang 097; Feng Yu 003; Bei Zhao; Zhenguo Ma (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Parallel Pipelined Architecture and Algorithm for Matrix Transposition Using Registers. - Bo Zhang 097; Zhenguo Ma; Wei Luo (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Accelerating Hierarchical Federated Learning with Adaptive Aggregation Frequency in Edge Computing. - Suo Chen; Zhenguo Ma; Zhiyuan Wang 002 (CNIOT, 2023)

Adaptive Batch Size for Federated Learning in Resource-Constrained Edge Computing. - Zhenguo Ma; Yang Xu 020; Hongli Xu; Zeyu Meng; Liusheng Huang; Yinxing Xue (IEEE Trans. Mob. Comput., 2023)

Adaptive Control of Local Updating and Model Compression for Efficient Federated Learning. - Yang Xu 020; Yunming Liao; Hongli Xu; Zhenguo Ma; Lun Wang; Jianchun Liu (IEEE Trans. Mob. Comput., 2023)

Optimised Serial Commutator FFT Architecture in Terms of Multiplexers. - Hongji Fang; Zhenguo Ma; Feng Yu 003; Bei Zhao; Bo Zhang 097 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Like Attracts Like: Personalized Federated Learning in Decentralized Edge Computing. - Zhenguo Ma; Yang Xu 020; Hongli Xu; Jianchun Liu; Yinxing Xue (IEEE Trans. Mob. Comput., 2024)

FedLC: Accelerating Asynchronous Federated Learning in Edge Computing. - Yang Xu 020; Zhenguo Ma; Hongli Xu; Suo Chen; Jianchun Liu; Yinxing Xue (IEEE Trans. Mob. Comput., 2024)

Enhancing Decentralized and Personalized Federated Learning With Topology Construction. - Suo Chen; Yang Xu 020; Hongli Xu; Zhenguo Ma; Zhiyuan Wang 002 (IEEE Trans. Mob. Comput., 2024)

Hier-FUN: Hierarchical Federated Learning and Unlearning in Heterogeneous Edge Computing. - Zhenguo Ma; Huaqing Tu; Li Zhou; Pengli Ji; Xiaoran Yan; Hongli Xu; Zhiyuan Wang 002; Suo Chen (IEEE Internet Things J., 2025)

Area-Efficient Pipeline Architecture for Serial Real-Valued Fast Fourier Transform. - Kun Li; Hongji Fang; Zhenguo Ma; Feng Yu 003; Bo Zhang 097; Qianjian Xing (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Mitigating Catastrophic Forgetting with Adaptive Transformer Block Expansion in Federated Fine-Tuning. - Yujia Huo; Jianchun Liu; Hongli Xu; Zhenguo Ma; Shilong Wang; Liusheng Huang (CoRR, 2025)

A Fast Floating-Point Multiply-Accumulator Optimized for Sparse Linear Algebra on FPGAs. - Kun Li; Xiangyu Hao; Zhenguo Ma; Feng Yu 003; Bo Zhang 097; Qianjian Xing (IEEE Trans. Very Large Scale Integr. Syst., 2025)