Zhen Liu

Affiliations:
  • Dublin City University, School of Electronic Engineering, Dublin, Ireland
  • Tsinghua University, Department of Computer Science and Technology, Beijing, China


According to our database1, Zhen Liu authored at least 15 papers between 2004 and 2010.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2010
SimNP: A Flexible Platform for the Simulation of Network Processing Systems.
Commun. Netw., 2010

Ultra-high throughput string matching for Deep Packet Inspection.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Power-Efficient Packet Classifier for Next-Generation Routers.
ERCIM News, 2009

Field-Based Branch Prediction for Packet Processing Engines.
Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009

Multi-Engine Packet Classification Hardware Accelerator.
Proceedings of the 18th International Conference on Computer Communications and Networks, 2009

2008
Revisiting the Cache Effect on Multicore Multithreaded Network Processors.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Low power architecture for high speed packet classification.
Proceedings of the 2008 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2008

2007
Hybrid cache architecture for high-speed packet processing.
IET Comput. Digit. Tech., 2007

2006
A scalable IPv6 route lookup scheme via dynamic variable-stride bitmap compression and path compression.
Comput. Commun., 2006

A Trace Driven Comparison of Latency Hiding Techniques for Network Processors.
Proceedings of IEEE International Conference on Communications, 2006

Optimal Deployment of Distributed Passive Measurement Monitors.
Proceedings of IEEE International Conference on Communications, 2006

Fuzzy Optimization for Security Sensors Deployment in Collaborative Intrusion Detection System.
Proceedings of the Fuzzy Systems and Knowledge Discovery, Third International Conference, 2006

2005
High Performance Embedded Route Lookup Coprocessor for Network Processors.
Proceedings of the Networking and Mobile Computing, Third International Conference, 2005

2004
A low-latency software-based route lookup implementation for network processors.
Proceedings of the 12th IEEE International Conference on Networks, 2004

FPGA implementation of hierarchical memory architecture for network processors.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004


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