A 40 Gbps optical receiver analog front-end in 65 nm CMOS. - Shun-Tien Chou; Shih-Hao Huang; Zheng-Hao Hong; Wei-Zen Chen (ISCAS, 2012)

A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery. - Zheng-Hao Hong; Wei-Zen Chen (A-SSCC, 2014)

A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS. - Shih-Hao Huang; Zheng-Hao Hong; Wei-Zen Chen (A-SSCC, 2014)

A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery. - Zheng-Hao Hong; Yao-Chia Liu; Wei-Zen Chen (IEEE J. Solid State Circuits, 2015)