Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window. - Chien-An Lai; Chung-Cheng Chou; Chi-Hsiang Weng; Zheng-Jun Lin; Pei-Ling Tseng; Chien-Fan Wang; Chih-Chen Wang; Chin-I Su; Wei-Chi Chen; Yu-Cheng Lin; Tong-Chern Ong; Chi Chang; et al. (A-SSCC, 2018)

An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance. - Chung-Cheng Chou; Zheng-Jun Lin; Pei-Ling Tseng; Chih-Feng Li; Chih-Yang Chang; Wei-Chi Chen; Yu-Der Chih; Tsung-Yung Jonathan Chang (ISSCC, 2018)

Deconstruction of Perception Verbs: Structure and Value. - Yan Liu; Zheng-Jun Lin; Ying Pan (ICMLC, 2019)

A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range. - Chung-Cheng Chou; Zheng-Jun Lin; Chien-An Lai; Chin-I Su; Pei-Ling Tseng; Wei-Chi Chen; Wu-Chin Tsai; Wen-Ting Chu; Tong-Chern Ong; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Circuits, 2020)