Worst Case Analysis of DRAM Latency in Multi-requestor Systems. - Zheng Pei Wu; Yogen Krish; Rodolfo Pellizzoni (RTSS, 2013)

A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems. - Yogen Krishnapillai; Zheng Pei Wu; Rodolfo Pellizzoni (ECRTS, 2014)

PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms. - Heechul Yun; Renato Mancuso 001; Zheng Pei Wu; Rodolfo Pellizzoni (RTAS, 2014)

A composable worst case latency analysis for multi-rank DRAM devices under open row policy. - Zheng Pei Wu; Rodolfo Pellizzoni; Danlu Guo (Real Time Syst., 2016)

Schedulability Analysis for Memory Bandwidth Regulated Multicore Real-Time Systems. - Gang Yao; Heechul Yun; Zheng Pei Wu; Rodolfo Pellizzoni; Marco Caccamo; Lui Sha (IEEE Trans. Computers, 2016)