A new method for model based frugal OPC. - Xiaolang Yan; Ye Chen; Zheng Shi 002; Yue Ma (ASP-DAC, 2005)

Full-IC manufacturability check based on dense silicon imaging. - Xiaolang Yan; Zheng Shi 002; Ye Chen; Yue Ma; Gensheng Gao (Sci. China Ser. F Inf. Sci., 2005)

An Automated and Fast OPC Algorithm for OPC-Aware Layout Design. - Ye Chen; Zheng Shi 002; Xiaolang Yan (ISQED, 2007)

A fully automated large-scale addressable test chip design with high reliability. - Bo Zhang; Weiwei Pan; Yongjun Zheng; Zheng Shi 002; Xiaolang Yan (ECCTD, 2011)

Using NMOS transistors as switches for accuracy and area-efficiency in large-scale addressable test array. - Weiwei Pan; Jie Ren; Yongjun Zheng; Zheng Shi 002; Xiaolang Yan (ISQED, 2011)

A sparse matrix model-based optical proximity correction algorithm with model-based mapping between segments and control sites. - Bin Lin 003; Xiaolang Yan; Zheng Shi 002; Yiwei Yang 003 (J. Zhejiang Univ. Sci. C, 2011)

Erratum to: A sparse matrix model-based optical proximity correction algorithm with model-based mapping between segments and control sites. - Bin Lin 003; Xiaolang Yan; Zheng Shi 002; Yiwei Yang 003 (J. Zhejiang Univ. Sci. C, 2011)

Array based HV/VH tree: an effective data structure for layout representation. - Jie Ren; Weiwei Pan; Yongjun Zheng; Zheng Shi 002; Xiaolang Yan (J. Zhejiang Univ. Sci. C, 2012)

A New Level-Set-Based Inverse Lithography Algorithm for Process Robustness Improvement with Attenuated Phase Shift Mask. - Zhen Geng; Zheng Shi 002; Xiaolang Yan; Kai-sheng Luo (CAD/Graphics, 2013)

Regularized level-set-based inverse lithography algorithm for IC mask synthesis. - Zhen Geng; Zheng Shi 002; Xiaolang Yan; Kai-sheng Luo (J. Zhejiang Univ. Sci. C, 2013)

SVM based layout retargeting for fast and regularized inverse lithography. - Kai-sheng Luo; Zheng Shi 002; Xiaolang Yan; Zhen Geng (J. Zhejiang Univ. Sci. C, 2014)

A New On-chip Signal Generator for Charge-Based Capacitance Measurement Circuit. - Xiaopeng Yu 002; Rong Qian Tian; Wen Lin Xu; Zheng Shi 002 (J. Electron. Test., 2015)

Fast Level-Set-Based Inverse Lithography Algorithm for Process Robustness Improvement and Its Application. - Zhen Geng; Zheng Shi 002; Xiaolang Yan; Kai-sheng Luo; Weiwei Pan (J. Comput. Sci. Technol., 2015)

Design and automatic generation of area-efficient ring oscillator based addressable test chips. - Xiaoxin Dou; Weiwei Pan; Zheng Shi 002; Yongjun Zheng (ASICON, 2017)

A novel layout automation flow to facilitate test chip design for standard cell characterization. - Ludan Yang; Weiwei Pan; Zheng Shi 002; Yongjun Zheng (ASICON, 2017)

Rate-Adaptive Protograph LDPC Codes for Multi-Level-Cell NAND Flash Memory. - Pingping Chen; Kui Cai 001; Zheng Shi 002 (IEEE Commun. Lett., 2018)

A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS. - Yun Fang; Xiaopeng Yu 002; Zheng Shi 002; Kiat Seng Yeo (Integr., 2018)

A CMOS Temperature Sensor With Versatile Readout Scheme and High Accuracy for Multi-Sensor Systems. - Zhong Tang; Yun Fang; Xiaopeng Yu 002; Zheng Shi 002; Nianxiong Tan (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An Untrimmed BJT-Based Temperature Sensor With Dynamic Current-Gain Compensation in 55-nm CMOS Process. - Zhong Tang; Yun Fang; Zhenyan Huang; Xiaopeng Yu 002; Zheng Shi 002; Nianxiong Tan (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Reliability-Oriented Startup Analysis of Injection-Locked Frequency Divider Based on Broken Symmetry Theory. - Yun Fang; Zhong Tang; Xiao-Peng Yu 002; Zheng Shi 002; Kiat Seng Yeo (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 1770-µm2 Leakage-Based Digital Temperature Sensor With Supply Sensitivity Suppression in 55-nm CMOS. - Zhong Tang; Yun Fang; Zheng Shi 002; Xiao-Peng Yu 002; Nianxiong Tan; Weiwei Pan (IEEE J. Solid State Circuits, 2020)

A Dynamic-Biased Resistor-Based CMOS Temperature Sensor With a Duty-Cycle-Modulated Output. - Zhong Tang; Yun Fang; Xiao-Peng Yu 002; Zheng Shi 002; Ling Lin; Nianxiong Nick Tan (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 1-V Diode-Based Temperature Sensor with a Resolution FoM of 3.1pJ•K2 in 55nm CMOS. - Zhong Tang; Yun Fang; Xiao-Peng Yu 002; Nianxiong Nick Tan; Zheng Shi 002; Pieter Harpe (CICC, 2021)

A BJT-Based CMOS Temperature Sensor With Duty-Cycle-Modulated Output and ±0.5°C (3σ) Inaccuracy From -40 °C to 125 °C. - Zhenyan Huang; Zhong Tang; Xiao-Peng Yu 002; Zheng Shi 002; Ling Lin; Nianxiong Nick Tan (IEEE Trans. Circuits Syst. II Express Briefs, 2021)