Zheng Yu

According to our database, Zheng Yu authored at least 6 papers between 2013 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process.

Zheng Yu, Zhiyi Yu, Xueqiu Yu, Ningxi Liu, Xiaoyang Zeng

IEEE Trans. Circuits Syst. II Express Briefs, 2014

A 16-Core Processor With Shared-Memory and Message-Passing Communications.

Zhiyi Yu, Ruijin Xiao, Kaidi You, Heng Quan, Peng Ou, Zheng Yu, Maofei He, Jiajie Zhang, Yan Ying, Haofan Yang, Jun Han, Xu Cheng, Zhang Zhang, Ming-e Jing, Xiaoyang Zeng

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013

Efficient distributed memory management in a multi-core H.264 decoder on FPGA.

Jiajie Zhang, Zheng Yu, Zhiyi Yu, Kexin Zhang, Zhonghai Lu, Axel Jantsch

Proceedings of the 2013 International Symposium on System on Chip, 2013

A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array.

Peng Ou, Jiajie Zhang, Heng Quan, Yi Li, Maofei He, Zheng Yu, Xueqiu Yu, Shile Cui, Jie Feng, Shikai Zhu, Jie Lin, Ming-e Jing, Xiaoyang Zeng, Zhiyi Yu

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A low power register file with asynchronously controlled read-isolation and software-directed write-discarding.

Zheng Yu, Jiajie Zhang, Xueqiu Yu, Xiaoyang Zeng, Zhiyi Yu

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

H.264 video parallel decoder on a 24-core processor.

Shikai Zhu, Zheng Yu, Shile Cui, Zhiyi Yu, Xiaoyang Zeng

Proceedings of the IEEE 10th International Conference on ASIC, 2013