H.264 video parallel decoder on a 24-core processor. - Shikai Zhu; Zheng Yu 001; Shile Cui; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

A low power register file with asynchronously controlled read-isolation and software-directed write-discarding. - Zheng Yu 001; Jiajie Zhang; Xueqiu Yu; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2013)

A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array. - Peng Ou; Jiajie Zhang; Heng Quan; Yi Li; Maofei He; Zheng Yu 001; Xueqiu Yu; Shile Cui; Jie Feng; Shikai Zhu; Jie Lin; Ming-e Jing; et al. (ISSCC, 2013)

Efficient distributed memory management in a multi-core H.264 decoder on FPGA. - Jiajie Zhang; Zheng Yu 001; Zhiyi Yu; Kexin Zhang; Zhonghai Lu; Axel Jantsch (ISSoC, 2013)

A 16-Core Processor With Shared-Memory and Message-Passing Communications. - Zhiyi Yu; Ruijin Xiao; Kaidi You; Heng Quan; Peng Ou; Zheng Yu 001; Maofei He; Jiajie Zhang; Yan Ying; Haofan Yang 001; Jun Han 003; Xu Cheng 002; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process. - Zheng Yu 001; Zhiyi Yu; Xueqiu Yu; Ningxi Liu; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2014)