Exploring architecture parameters for dual-output LUT based FPGAs. - Zhenghong Jiang; Colin Yu Lin; Liqun Yang; Fei Wang; Haigang Yang (FPL, 2014)

A technology mapper for depth-constrained FPGA logic cells. - Zhenghong Jiang; Grace Zgheib; Colin Yu Lin; David Novo; Zhihong Huang; Liqun Yang; Haigang Yang; Paolo Ienne (FPL, 2015)

FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels. - Colin Yu Lin; Zhenghong Jiang; Cheng Fu; Hayden Kwok-Hay So; Haigang Yang (SIGARCH Comput. Archit. News, 2016)

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. - Zhihong Huang; Xing Wei; Grace Zgheib; Wei Li 008; Yu Lin; Zhenghong Jiang; Kaihui Tu; Paolo Ienne; Haigang Yang (FPGA, 2017)

High-level synthesis with timing-sensitive information flow enforcement. - Zhenghong Jiang; Steve Dai; G. Edward Suh; Zhiru Zhang (ICCAD, 2018)

Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES. - Zhenghong Jiang; Hanchen Jin; G. Edward Suh; Zhiru Zhang (DAC, 2019)

Efficient Loop Closure Detection Method for Lidar SLAM in Challenging Environment. - Yang Li; Wanbiao Lin; Tianjun Zha; Zhenghong Jiang; Peiwen Li; Lei Sun 001 (CRC, 2021)

Simulation of Electronic Equipment Control Method Based on Improved Neural Network Algorithm. - Zhenghong Jiang; Chunrong Zhou (ICATCI (2), 2022)

Application of improved Naive Bayes classification algorithm in 5G signaling analysis. - Wanwan Wang; Yu Duan; Longhan Cao; Zhenghong Jiang (J. Supercomput., 2023)

Multi-objective task scheduling in cloud-fog computing using reptile search algorithm. - Zhenghong Jiang; Chunrong Zhou; Qiang Chen (Int. J. Knowl. Based Intell. Eng. Syst., 2025)