A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge. - Kai Li 024; Junzhuo Zhou; Yuhang Wang; Junyi Luo; Zhengke Yang; Shuxin Yang; Wei Mao 002; Mingqiang Huang; Hao Yu 001 (DATE, 2022)

A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA. - Mingqiang Huang; Yucen Liu; Quan Cheng; Shuxin Yang; Kai Li 024; Junyi Luo; Zhengke Yang; Qiufeng Li; Hao Yu 001; Changhai Man (FPGA, 2022)

A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing. - Kai Li 024; Wei Mao 002; Junzhuo Zhou; Boyu Li; Zhengke Yang; Shuxing Yang; Laimin Du; Sixiao Huang; Hao Yu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping. - Quan Cheng; Longyang Lin; Mingqiang Huang; Qiufeng Li; Zhengke Yang; Liuyao Dai; Hao Yu 001; Yu-Jen Chen; Yiyu Shi 001; Masanori Hashimoto (A-SSCC, 2024)

A 22nm 29.3TOPS/W End-to-End CIM-Utilization-Aware Accelerator with Reconfigurable 4D-CIM Mapping and Adaptive Feature Reuse for Diverse CNNs and Transformers. - Jin Wang; Moxiao Lou; Zhengke Yang; Ruijie Peng; Humiao Li; Weirong Dong; Haoran Lyu; Yida Li; Jiamin Li; Hao Yu 001; Jerald Yoo; Longyang Lin (CICC, 2025)

Efficient Calibration for RRAM-based In-Memory Computing using DoRA. - Weirong Dong; Kai Zhou; Zhen Kong; Quan Cheng; Junkai Huang; Zhengke Yang; Masanori Hashimoto; Longyang Lin (CoRR, 2025)