Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation. - Zhengya Zhang; Lara Dolecek; Borivoje Nikolic; Venkat Anantharam; Martin J. Wainwright (GLOBECOM, 2006)

Analysis of Absorbing Sets for Array-Based LDPC Codes. - Lara Dolecek; Zhengya Zhang; Venkat Anantharam; Martin J. Wainwright; Borivoje Nikolic (ICC, 2007)

Quantization Effects in Low-Density Parity-Check Decoders. - Zhengya Zhang; Lara Dolecek; Martin J. Wainwright; Venkat Anantharam; Borivoje Nikolic (ICC, 2007)

Peak-to-Average Power Ratio Reduction in an FDM Broadcast System. - Zhengya Zhang; Renaldi Winoto; Ahmad Bahai; Borivoje Nikolic (SiPS, 2007)

Lowering LDPC Error Floors by Postprocessing. - Zhengya Zhang; Lara Dolecek; Borivoje Nikolic; Venkat Anantharam; Martin J. Wainwright (GLOBECOM, 2008)

Error floors in LDPC codes: Fast simulation, bounds and hardware emulation. - Pamela Lee; Lara Dolecek; Zhengya Zhang; Venkat Anantharam; Borivoje Nikolic; Martin J. Wainwright (ISIT, 2008)

Predicting error floors of structured LDPC codes: deterministic bounds and estimates. - Lara Dolecek; Pamela Lee; Zhengya Zhang; Venkat Anantharam; Borivoje Nikolic; Martin J. Wainwright (IEEE J. Sel. Areas Commun., 2009)

Design of LDPC decoders for improved low error rate performance: quantization and algorithm choices. - Zhengya Zhang; Lara Dolecek; Borivoje Nikolic; Venkat Anantharam; Martin J. Wainwright (IEEE Trans. Commun., 2009)

An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors. - Zhengya Zhang; Venkat Anantharam; Martin J. Wainwright; Borivoje Nikolic (IEEE J. Solid State Circuits, 2010)

Analysis of absorbing sets and fully absorbing sets of array-based LDPC codes. - Lara Dolecek; Zhengya Zhang; Venkat Anantharam; Martin J. Wainwright; Borivoje Nikolic (IEEE Trans. Inf. Theory, 2010)

A confidence-driven model for error-resilient computing. - Chia-Hsiang Chen; Yejoong Kim; Zhengya Zhang; David T. Blaauw; Dennis Sylvester; Helia Naeimi; Sumeet Sandhu (DATE, 2011)

Hardware acceleration of iterative image reconstruction for X-ray computed tomography. - Jung Kuk Kim; Zhengya Zhang; Jeffrey A. Fessler (ICASSP, 2011)

LDPC decoder architecture for high-data rate personal-area networks. - Matthew Weiner; Borivoje Nikolic; Zhengya Zhang (ISCAS, 2011)

Absorbing set spectrum approach for practical code design. - Jiadong Wang; Lara Dolecek; Zhengya Zhang; Richard D. Wesel (ISIT, 2011)

Reconfigurable architecture and automated design flow for rapid FPGA-based LDPC code emulation. - Haoran Li; Youn Sung Park; Zhengya Zhang (FPGA, 2012)

High-throughput architecture and implementation of regular (2, dc) nonbinary LDPC decoders. - Yaoyu Tao; Youn Sung Park; Zhengya Zhang (ISCAS, 2012)

A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM. - Youn Sung Park; David T. Blaauw; Dennis Sylvester; Zhengya Zhang (VLSIC, 2012)

The Cycle Consistency Matrix Approach to LDPC Absorbing Sets in Separable Circulant-Based Codes - Jiadong Wang; Lara Dolecek; Zhengya Zhang; Richard D. Wesel (CoRR, 2012)

Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems. - Dongsuk Jeon; Mingoo Seok; Zhengya Zhang; David T. Blaauw; Dennis Sylvester (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Forward-Projection Architecture for Fast Iterative Image Reconstruction in X-Ray CT. - Jung Kuk Kim; Jeffrey A. Fessler; Zhengya Zhang (IEEE Trans. Signal Process., 2012)

An FPGA-based transient error simulator for evaluating resilient system designs (abstract only). - Chia-Hsiang Chen; Shiming Song 002; Zhengya Zhang (FPGA, 2013)

A low-power VGA full-frame feature extraction processor. - Dongsuk Jeon; Yejoong Kim; Inhee Lee 001; Zhengya Zhang; David T. Blaauw; Dennis Sylvester (ICASSP, 2013)

Efficient in situ error detection enabling diverse path coverage. - Chia-Hsiang Chen; Yaoyu Tao; Zhengya Zhang (ISCAS, 2013)

Minimum supply voltage for sequential logic circuits in a 22nm technology. - Chia-Hsiang Chen; Keith A. Bowman; Charles Augustine; Zhengya Zhang; Jim Tschanz (ISLPED, 2013)

A 470mV 2.7mW feature extraction-accelerator for micro-autonomous vehicle navigation in 28nm CMOS. - Dongsuk Jeon; Yejoong Kim; Inhee Lee 001; Zhengya Zhang; David T. Blaauw; Dennis Sylvester (ISSCC, 2013)

A 1.15Gb/s fully parallel nonbinary LDPC decoder with fine-grained dynamic clock gating. - Youn Sung Park; Yaoyu Tao; Zhengya Zhang (ISSCC, 2013)

Memristive devices for stochastic computing. - Siddharth Gaba; Phil Knag; Zhengya Zhang; Wei Lu 003 (ISCAS, 2014)

24.3 An implantable 64nW ECG-monitoring mixed-signal SoC for arrhythmia diagnosis. - Dongsuk Jeon; Yen-Po Chen; Yoonmyung Lee; Yejoong Kim; Zhiyoong Foo; Grant H. Kruger; Hakan Oral; Omer Berenfeld; Zhengya Zhang; David T. Blaauw; Dennis Sylvester (ISSCC, 2014)

27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder. - Tai-Chuan Ou; Zhengya Zhang; Marios C. Papaefthymiou (ISSCC, 2014)

3.2Gbps channel-adaptive configurable MIMO detector for multi-mode wireless communication. - Farhana Sheikh; Chia-Hsiang Chen; Dongmin Yoon; Borislav Alexandrov; Keith A. Bowman; Anthony Chun; Hossein Alavi; Zhengya Zhang (SiPS, 2014)

A 6.67mW sparse coding ASIC enabling on-chip learning and inference. - Jung Kuk Kim; Phil Knag; Thomas Chen 003; Zhengya Zhang (VLSIC, 2014)

A 4.68Gb/s belief propagation polar decoder with bit-splitting register file. - Youn Sung Park; Yaoyu Tao; Shuanghong Sun; Zhengya Zhang (VLSIC, 2014)

An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS. - Dongsuk Jeon; Michael B. Henry; Yejoong Kim; Inhee Lee 001; Zhengya Zhang; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2014)

Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM. - Youn Sung Park; David T. Blaauw; Dennis Sylvester; Zhengya Zhang (IEEE J. Solid State Circuits, 2014)

Efficient Hardware Architecture for Sparse Coding. - Jung Kuk Kim; Phil Knag; Thomas Chen 003; Zhengya Zhang (IEEE Trans. Signal Process., 2014)

Design and Evaluation of Confidence-Driven Error-Resilient Systems. - Chia-Hsiang Chen; David T. Blaauw; Dennis Sylvester; Zhengya Zhang (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors. - Tai-Chuan Ou; Zhengya Zhang; Marios C. Papaefthymiou (A-SSCC, 2015)

18.7 A 2.4mm2 130mW MMSE-nonbinary-LDPC iterative detector-decoder for 4×4 256-QAM MIMO in 65nm CMOS. - Chia-Hsiang Chen; Wei Tang 010; Zhengya Zhang (ISSCC, 2015)

A 640M pixel/s 3.65mW sparse event-driven neuromorphic object recognition processor with on-chip learning. - Jung Kuk Kim; Phil Knag; Thomas Chen 003; Zhengya Zhang (VLSIC, 2015)

1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks. - Shengshuo Lu; Zhengya Zhang; Marios C. Papaefthymiou (VLSIC, 2015)

An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring. - Yen-Po Chen; Dongsuk Jeon; Yoonmyung Lee; Yejoong Kim; Zhiyoong Foo; Inhee Lee 001; Nicholas B. Langhals; Grant H. Kruger; Hakan Oral; Omer Berenfeld; Zhengya Zhang; David T. Blaauw; et al. (IEEE J. Solid State Circuits, 2015)

A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding. - Phil Knag; Jung Kuk Kim; Thomas Chen 003; Zhengya Zhang (IEEE J. Solid State Circuits, 2015)

A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating. - Youn Sung Park; Yaoyu Tao; Zhengya Zhang (IEEE J. Solid State Circuits, 2015)

An FPGA-Based Transient Error Simulator for Resilient Circuit and System Design and Evaluation. - Chia-Hsiang Chen; Shiming Song 002; Zhengya Zhang (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Error patterns in belief propagation decoding of polar codes and their mitigation methods. - Shuanghong Sun; Sung-Gun Cho; Zhengya Zhang (ACSSC, 2016)

A 5.5GHz 0.84TOPS/mm2 neural network engine with stream architecture and resonant clock mesh. - Shengshuo Lu; Zhengya Zhang; Marios C. Papaefthymiou (A-SSCC, 2016)

A 180 GHz prototype for a geostationary microwave imager/sounder-GeoSTAR-III. - Todd Gaier; Pekka Kangaslahti; Bjorn Lambrigtsen; Isaac Ramos-Pérez; Alan B. Tanner; Darren McKague; Christopher Ruf; Michael J. Flynn; Zhengya Zhang; Roger Backhus; David Austerberry (IGARSS, 2016)

Architecture and optimization of high-throughput belief propagation decoding of polar codes. - Shuanghong Sun; Zhengya Zhang (ISCAS, 2016)

A Simple Generic Attack on Text Captchas. - Haichang Gao; Jeff Yan; Fang Cao; Zhengya Zhang; Lei Lei; Mengyun Tang; Ping Zhang; Xin Zhou; Xuqin Wang; Jiawei Li (NDSS, 2016)

A 1.40mm2 141mW 898GOPS sparse neuromorphic processor in 40nm CMOS. - Phil Knag; Chester Liu; Zhengya Zhang (VLSI Circuits, 2016)

A 0.58mm2 2.76Gb/s 79.8pJ/b 256-QAM massive MIMO message-passing detector. - Wei Tang 010; Chia-Hsiang Chen; Zhengya Zhang (VLSI Circuits, 2016)

Robustness of text-based completely automated public turing test to tell computers and humans apart. - Haichang Gao; Xuqin Wang; Fang Cao; Zhengya Zhang; Lei Lei; Jiao Qi; Xiyang Liu (IET Inf. Secur., 2016)

3.2 Gbps Channel-Adaptive Configurable MIMO Detector for Multi-Mode Wireless Communication. - Farhana Sheikh; Chia-Hsiang Chen; Dongmin Yoon; Borislav Alexandrov; Keith A. Bowman; Anthony Chun; Hossein Alavi; Zhengya Zhang (J. Signal Process. Syst., 2016)

A 2.56mm2 718GOPS configurable spiking convolutional sparse coding processor in 40nm CMOS. - Chester Liu; Sung-Gun Cho; Zhengya Zhang (A-SSCC, 2017)

A 1.25pJ/bit 0.048mm2 AES core with DPA resistance for IoT devices. - Shengshuo Lu; Zhengya Zhang; Marios C. Papaefthymiou (A-SSCC, 2017)

Post-Processing Methods for Improving Coding Gain in Belief Propagation Decoding of Polar Codes. - Shuanghong Sun; Sung-Gun Cho; Zhengya Zhang (GLOBECOM, 2017)

3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation. - Ziyun Li; Qing Dong 001; Mehdi Saligane; Benjamin P. Kempke; Shijia Yang; Zhengya Zhang; Ronald G. Dreslinski; Dennis Sylvester; David T. Blaauw; Hun-Seok Kim (ISSCC, 2017)

20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS. - Hsi-Shou Wu; Zhengya Zhang; Marios C. Papaefthymiou (ISSCC, 2017)

Designing Practical Polar Codes Using Simulation-Based Bit Selection. - Shuanghong Sun; Zhengya Zhang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2017)

A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging. - John Bell; Phil Knag; Shuanghong Sun; Yong Lim; Thomas Chen 003; Jeffrey Fredenburg; Chia-Hsiang Chen; Chunyang Zhai; Aaron Z. Rocca; Nicholas Collins; Andres Tamez; Jorge Pernillo; et al. (IEEE J. Solid State Circuits, 2017)

Editorial. - Krishnendu Chakrabarty; Massimo Alioto; Bevan M. Baas; Chirn Chye Boon; Meng-Fan Chang; Naehyuck Chang; Yao-Wen Chang; Chip-Hong Chang; Shih-Chieh Chang; Poki Chen; Masud H. Chowdhury; Pasquale Corsonello; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Inference and Learning Hardware Architecture for Neuro- Inspired Sparse Coding Algoerithm. - Chester Liu; Zhengya Zhang (BioCAS, 2018)

LEIA: A 2.05mm2 140mW lattice encryption instruction accelerator in 40nm CMOS. - Shiming Song 002; Wei Tang 010; Thomas Chen 003; Zhengya Zhang (CICC, 2018)

A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks. - Hsi-Shou Wu; Zhengya Zhang; Marios C. Papaefthymiou (ESSCIRC, 2018)

A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI. - Wei Tang 010; Hemanth Prabhu; Liang Liu 002; Viktor Öwall; Zhengya Zhang (ISSCC, 2018)

Optimizing a Fuzzy Equivalent Sliding Mode Control Applied to Servo Drive Systems. - Zhengya Zhang; Matilde Santos 001 (SOCO-CISIS-ICEUTE, 2018)

A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles. - Ziyun Li; Qing Dong 001; Mehdi Saligane; Benjamin P. Kempke; Luyao Gong; Zhengya Zhang; Ronald G. Dreslinski; Dennis Sylvester; David T. Blaauw; Hun-Seok Kim (IEEE J. Solid State Circuits, 2018)

A 2.56-mm2 718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS. - Chester Liu; Sung-Gun Cho; Zhengya Zhang (IEEE J. Solid State Circuits, 2018)

A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link. - Shiming Song 002; Kyojin David Choo; Thomas Chen 003; Sunmin Jang; Michael P. Flynn; Zhengya Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Field-Programmable Crossbar Array (FPCA) for Reconfigurable Computing. - Mohammed Affan Zidan; YeonJoo Jeong; Jong Hoon Shin; Chao Du; Zhengya Zhang; Wei D. Lu (IEEE Trans. Multi Scale Comput. Syst., 2018)

An Sram-Based Accelerator for Solving Partial Differential Equations. - Thomas Chen 003; Jacob Botimer; Teyuh Chou; Zhengya Zhang (CICC, 2019)

A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS. - Sung-Gun Cho; Edith Beigné; Zhengya Zhang (CICC, 2019)

CASCADE: Connecting RRAMs to Extend Analog Dataflow In An End-To-End In-Memory Processing Paradigm. - Teyuh Chou; Wei Tang 010; Jacob Botimer; Zhengya Zhang (MICRO, 2019)

A 3.25Gb/s, 13.2pJ/b, 0.64mm2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS. - Yaoyu Tao; Sung-Gun Cho; Zhengya Zhang (VLSI Circuits, 2019)

SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS. - Jie-Fang Zhang; Ching-En Lee; Chester Liu; Yakun Sophia Shao; Stephen W. Keckler; Zhengya Zhang (VLSI Circuits, 2019)

A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification. - Thomas Chen 003; Ching-En Lee; Chester Liu; Zhengya Zhang (IEEE J. Solid State Circuits, 2019)

A 2.4-mm2 130-mW MMSE-Nonbinary LDPC Iterative Detector Decoder for 4×4 256-QAM MIMO in 65-nm CMOS. - Wei Tang 010; Chia-Hsiang Chen; Zhengya Zhang (IEEE J. Solid State Circuits, 2019)

Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes. - Yaoyu Tao; Shuanghong Sun; Zhengya Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. - Massimo Alioto; Magdy S. Abadir; Tughrul Arslan; Chirn Chye Boon; Andreas Burg 001; Chip-Hong Chang; Meng-Fan Chang; Yao-Wen Chang; Poki Chen; Pasquale Corsonello; Paolo Crovetti; Shiro Dosho; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2019)

QuickNN: Memory and Performance Optimization of k-d Tree Based Nearest Neighbor Search for 3D Point Clouds. - Reid Pinkham; Shuqing Zeng; Zhengya Zhang (HPCA, 2020)

Control of Magnetically-Driven Screws in a Viscoelastic Medium. - Zhengya Zhang; Anke Klingner; Sarthak Misra; Islam S. M. Khalil (IROS, 2020)

A 1.87-mm2 56.9-GOPS Accelerator for Solving Partial Differential Equations. - Thomas Chen 003; Jacob Botimer; Teyuh Chou; Zhengya Zhang (IEEE J. Solid State Circuits, 2020)

A 256Gb/s/mm-shoreline AIB-Compatible 16nm FinFET CMOS Chiplet for 2.5D Integration with Stratix 10 FPGA on EMIB and Tiling on Silicon Interposer. - Chester Liu; Jacob Botimer; Zhengya Zhang (CICC, 2021)

DNC-Aided SCL-Flip Decoding of Polar Codes. - Yaoyu Tao; Zhengya Zhang (GLOBECOM, 2021)

HiMA: A Fast and Scalable History-based Memory Access Engine for Differentiable Neural Computer. - Yaoyu Tao; Zhengya Zhang (MICRO, 2021)

Point-X: A Spatial-Locality-Aware Architecture for Energy-Efficient Graph-Based Point-Cloud Deep Learning. - Jie-Fang Zhang; Zhengya Zhang (MICRO, 2021)

Exploration of Energy-Efficient Architecture for Graph-Based Point-Cloud Deep Learning. - Jie-Fang Zhang; Zhengya Zhang (SiPS, 2021)

PETRA: A 22nm 6.97TFLOPS/W AIB-Enabled Configurable Matrix and Convolution Accelerator Integrated with an Intel Stratix 10 FPGA. - Sung-Gun Cho; Wei Tang 010; Chester Liu; Zhengya Zhang (VLSI Circuits, 2021)

VOTA: A 2.45TFLOPS/W Heterogeneous Multi-Core Visual Object Tracking Accelerator Based on Correlation Filters. - Junkang Zhu; Wei Tang 010; Ching-En Lee; Haolei Ye; Eric McCreath; Zhengya Zhang (VLSI Circuits, 2021)

Near-Sensor Distributed DNN Processing for Augmented and Virtual Reality. - Reid Pinkham; Andrew Berkovich; Zhengya Zhang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2021)

A 0.58-mm2 2.76-Gb/s 79.8-pJ/b 256-QAM Message-Passing Detector for a 128 × 32 Massive MIMO Uplink System. - Wei Tang 010; Chia-Hsiang Chen; Zhengya Zhang (IEEE J. Solid State Circuits, 2021)

A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture. - Yaoyu Tao; Sung-Gun Cho; Zhengya Zhang (IEEE J. Solid State Circuits, 2021)

SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference. - Jie-Fang Zhang; Ching-En Lee; Chester Liu; Yakun Sophia Shao; Stephen W. Keckler; Zhengya Zhang (IEEE J. Solid State Circuits, 2021)

NetFlex: A 22nm Multi-Chiplet Perception Accelerator in High-Density Fan-Out Wafer-Level Packaging. - Teyuh Chou; Wei Tang 010; Mihai D. Rotaru; Chester Liu; Rahul Dutta; Sharon Lim Pei Siang; David Ho Soon Wee; Surya Bhattacharya; Zhengya Zhang (VLSI Technology and Circuits, 2022)

An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. - Justin M. Correll; Lu Jie 001; Seungheun Song; Seungjong Lee; Junkang Zhu; Wei Tang 010; Luke Wormald; Jack Erhardt; Nicolas Breil; Roger Quon; Deepak Kamalanathan; Siddarth A. Krishnan; et al. (VLSI Technology and Circuits, 2022)

VOTA: A Heterogeneous Multicore Visual Object Tracking Accelerator Using Correlation Filters. - Junkang Zhu; Wei Tang 010; Ching-En Lee; Haolei Ye; Eric McCreath; Zhengya Zhang (IEEE J. Solid State Circuits, 2022)

TAICHI: A Tiled Architecture for In-Memory Computing and Heterogeneous Integration. - Xinxin Wang 002; Reid Pinkham; Mohammed Affan Zidan; Fan-Hsuan Meng; Michael P. Flynn; Zhengya Zhang; Wei D. Lu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

eNODE: Energy-Efficient and Low-Latency Edge Inference and Training of Neural ODEs. - Junkang Zhu; Yaoyu Tao; Zhengya Zhang (HPCA, 2023)

AR-PIM: An Adaptive-Range Processing-in-Memory Architecture. - Teyuh Chou; Fernando García-Redondo; Paul N. Whatmough; Zhengya Zhang (ISLPED, 2023)

Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. - Wei Tang 010; Sung-Gun Cho; Tim Tri Hoang; Jacob Botimer; Wei Qiang Zhu; Ching-Chi Chang; Cheng-Hsun Lu; Junkang Zhu; Yaoyu Tao; Tianyu Wei; Naomi Kavi Motwani; Mani Yalamanchi; et al. (VLSI Technology and Circuits, 2023)

ANSA: Adaptive Near-Sensor Architecture for Dynamic DNN Processing in Compact Form Factors. - Reid Pinkham; Jack Erhardt; Barbara De Salvo; Andrew Berkovich; Zhengya Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Design Approach for Die-to-Die Interfaces to Enable Energy-Efficient Chiplet Systems. - Vikram Jain; Wei Tang 010; Zuoguo Wu; Viansa Schmulbach; Yakun Sophia Shao; Zhengya Zhang; Borivoje Nikolic (ISLPED, 2024)

2.8 A 21.9ns 15.7 Gbps/mm² (128,15) BOSS FEC Decoder for 5G/6G URLLC Applications. - Dongyun Kam; Sangbu Yun; Jeongwon Choe; Zhengya Zhang; Namyoon Lee; Youngjoo Lee (ISSCC, 2024)

An 11.4mm2 40.2Gbps 17.4pJ/b/Iteration Soft-Decision Open Forward Error Correction Decoder for Optical Communications. - Cheng-Hsun Lu; Wei Tang; Jiyoon Han; Zhengya Zhang (VLSI Technology and Circuits, 2024)

Tiled Beamspace Processing for Scaling mmWave Massive MU-MIMO. - Jiyoon Han; Canan Cebeci; Wei Tang; Zhengya Zhang; Upamanyu Madhow (VTC Fall, 2024)

TT-CIM: Tensor Train Decomposition for Neural Network in RRAM-Based Compute-in-Memory Systems. - Fan-Hsuan Meng; Yuting Wu; Zhengya Zhang; Wei D. Lu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. - Wei Tang 010; Sung-Gun Cho; Tim Tri Hoang; Jacob Botimer; Wei Qiang Zhu; Ching-Chi Chang; Cheng-Hsun Lu; Junkang Zhu; Yaoyu Tao; Tianyu Wei; Naomi Kavi Motwani; Mani Yalamanchi; et al. (IEEE J. Solid State Circuits, 2024)

TetriX: Flexible Architecture and Optimal Mapping for Tensorized Neural Network Processing. - Jie-Fang Zhang; Cheng-Hsun Lu; Zhengya Zhang (IEEE Trans. Computers, 2024)

Practical MU-MIMO Detection and LDPC Decoding Through Digital Annealing. - Po-Shao Chen; Wei Tang; Zhengya Zhang (DATE, 2025)

Panacea: Novel DNN Accelerator using Accuracy-Preserving Asymmetric Quantization and Energy-Saving Bit-Slice Sparsity. - Dongyun Kam; Myeongji Yun; Sunwoo Yoo; Seungwoo Hong; Zhengya Zhang; Youngjoo Lee (HPCA, 2025)

HiPER: Hierarchically-Composed Processing for Efficient Robot Learning-Based Control. - Justin Ting; Minsik Kim 006; Junkang Zhu; Haotian Sheng; Zhengya Zhang (ISCA, 2025)

25.1 A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100% Solvability and 31.7μs Solution Time. - Evangelos Dikopoulos; Ying-Tuan Hsu; Luke Wormald; Wei Tang 010; Zhengya Zhang; Michael P. Flynn (ISSCC, 2025)

Energy-Efficient Parallel Interconnects for Chiplet Integration. - Wei Tang 010; Chester Liu; Zhengya Zhang (IEEE Micro, 2025)

A cross-matrix arbiter PUF with high reliability and ML-resistance for IoT device security. - Zhangqing He; Junming Zhang; Xinrui Zhu; Siyu Luo; Zhengya Zhang; Zhou Huang (Microelectron. J., 2025)

SteROI-D: System Design and Mapping for Stereo Depth Inference on Regions of Interest. - Jack Erhardt; Ziang Li; Reid Pinkham; Andrew Berkovich; Zhengya Zhang (CoRR, 2025)

Adaptive Attention-Based Model for 5G Radio-based Outdoor Localization. - Ilayda Yaman; Guoda Tian; Fredrik Tufvesson; Ove Edfors; Zhengya Zhang; Liang Liu 002 (CoRR, 2025)

RXO-LDPC: A Physics-Inspired Relaxation Oscillator-Based Solver Leveraging Six-Body Spin Interactions for Soft Decoding of LDPC Codes. - Evangelos Dikopoulos; Luke Wormald; Ying-Tuan Hsu; Wei Tang 010; Po-Shao Chen; Zhengya Zhang; Michael P. Flynn (IEEE J. Solid State Circuits, 2025)

An 8-bit 20.7 TOPS/W Multilevel Cell ReRAM Macro With ADC-Assisted Bit-Serial Processing. - Justin M. Correll; Lu Jie 001; Seungheun Song; Seungjong Lee; Junkang Zhu; Wei Tang 010; Luke Wormald; Jack Erhardt; Nicolas Breil; Roger Quon; Deepak Kamalanathan; Siddarth A. Krishnan; et al. (IEEE J. Solid State Circuits, 2025)