Analysis and Design of Energy Efficient Time Domain Signal Processing. - Zhengyu Chen 002; Jie Gu 001 (ISLPED, 2016)

An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. - Zhengyu Chen 002; Jie Gu 001 (A-SSCC, 2018)

R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. - Zhengyu Chen 002; Hai Zhou 001; Jie Gu 001 (ICCD, 2018)

A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design. - Zhengyu Chen 002; Huanyu Wang; Geng Xie; Jie Gu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing. - Zhengyu Chen 002; Hai Zhou 001; Jie Gu 001 (DAC, 2019)

A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput. - Zhengyu Chen 002; Jie Gu 001 (ISSCC, 2019)

A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation. - Zhengyu Chen 002; Jie Gu 001 (IEEE J. Solid State Circuits, 2019)

R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction. - Zhengyu Chen 002; Hai Zhou 001; Jie Gu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices. - Zhengyu Chen 002; Sihua Fu; Qiankai Cao; Jie Gu 001 (VLSI Circuits, 2020)

15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency. - Zhengyu Chen 002; Xi Chen 099; Jie Gu 001 (ISSCC, 2021)

High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing. - Zhengyu Chen 002; Jie Gu 001 (IEEE J. Solid State Circuits, 2021)

AI SoC Design Challenges in the Foundation Model Era. - Zhengyu Chen 002; Dawei Huang; Mingran Wang; Bowen Yang; Jinuk Luke Shin; Changran Hu; Bo Li 005; Raghu Prabhakar; Gao Deng; Yongning Sheng; Sihua Fu; Lu Yuan; et al. (CICC, 2023)

SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts. - Raghu Prabhakar; Ram Sivaramakrishnan; Darshan Gandhi; Yun Du; Mingran Wang; Xiangyu Song; Kejie Zhang; Tianren Gao; Angela Wang; Xiaoyan Li; Yongning Sheng; Joshua Brot; et al. (MICRO, 2024)

Composition of Experts on the SN40L Reconfigurable Dataflow Unit. - Raghu Prabhakar; Ram Sivaramakrishnan; Darshan Gandhi; Yun Du; Mingran Wang; Xiangyu Song; Kejie Zhang; Tianren Gao; Angela Wang; Xiaoyan Li; Joshua Brot; Calvin Leung; et al. (IEEE Micro, 2024)

Modeling, Design and In-situ Demonstration of Bio-inspired Central Pattern Generator and Neuromorphic Computing Circuits for Complex Kinematic Control of Quadruped Robots. - Qiankai Cao; Yuhao Ju; Zhiwei Zhong; Zhengyu Chen 002; Jie Gu 001 (ACM Great Lakes Symposium on VLSI, 2025)