Fast Performance Evaluation for Analog Circuit Synthesis Frameworks. - Zhenxin Zhao; Tuotian Liao; Lihong Zhang (ISCAS, 2018)

Graph-Grammar-Based Analog Circuit Topology Synthesis. - Zhenxin Zhao; Lihong Zhang (ISCAS, 2019)

Placement with Sequence-Pair-Driven TCG for Advanced Analog Constraints. - Lian He; Zhenxin Zhao; Yuanzhu Chen 001; Lihong Zhang (CCECE, 2020)

Advanced Transitive-Closure-Graph-Based Placement Representation for Analog Layout Design. - Lian He; Zhenxin Zhao; Yuanzhu Chen 001; Lihong Zhang (ICECS, 2020)

Deep Reinforcement Learning for Analog Circuit Sizing. - Zhenxin Zhao; Lihong Zhang (ISCAS, 2020)

An Automated Topology Synthesis Framework for Analog Integrated Circuits. - Zhenxin Zhao; Lihong Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis. - Zhenxin Zhao; Lihong Zhang (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Deep Reinforcement Learning for Analog Circuit Structure Synthesis. - Zhenxin Zhao; Lihong Zhang (DATE, 2022)

Fogging-Effect-Aware Mixed-Signal IC Placement with Reinforcement Learning. - Mohammad Hajijafari; Mehrnaz Ahmadi; Zhenxin Zhao; Lihong Zhang (ISCAS, 2022)

Reinforcement-Learning-based Mixed-Signal IC Placement for Fogging Effect Control. - Mohammad Hajijafari; Mehrnaz Ahmadi; Zhenxin Zhao; Lihong Zhang (ISQED, 2022)

Analog Integrated Circuit Topology Synthesis With Deep Reinforcement Learning. - Zhenxin Zhao; Lihong Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Signal-Division-Aware Analog Circuit Topology Synthesis Aided by Transfer Learning. - Zhenxin Zhao; Jiang Luo; Jun Liu 027; Lihong Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Acceleration for Efficient Automated Generation of Operational Amplifiers. - Zhenxin Zhao; Jun Liu; Lihong Zhang (Sensors, 2024)

Automated Topology Synthesis of Analog Integrated Circuits With Frequency Compensation. - Zhenxin Zhao; Jun Liu 027; Wen-Sheng Zhao; Lihong Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)