A VLSI Array Processing Oriented Fast Fourier Transform Algorithm and Hardware Implementation. - Zhenyu Liu 001; Yang Song 002; Takeshi Ikenaga; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Enhanced Partial Distortion Sorting Fast Motion Estimation Algorithm for Low-Power Applications. - Yang Song 002; Takeshi Ikenaga; Satoshi Goto; Zhenyu Liu 001 (APCCAS, 2006)

Low-Pass Filter Based Vlsi Oriented Variable Block Size Motion Estimation Algorithm for H.264. - Zhenyu Liu 001; Yang Song 002; Takeshi Ikenaga; Satoshi Goto (ICASSP (2), 2006)

System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV. - Kouichi Kumagai; Changqi Yang; Hitoshi Izumino; Nobuyuki Narita; Keisuke Shinjo; Shin-ichi Iwashita; Yuji Nakaoka; Tomohiro Kawamura; Hideo Komabashiri; Tsukasa Minato; Atsushi Ambo; Takamasa Suzuki; et al. (ISSCC, 2006)

A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC. - Zhenyu Liu 001; Yang Song 002; Takeshi Ikenaga; Satoshi Goto (IEICE Trans. Electron., 2006)

Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC. - Yang Song 002; Zhenyu Liu 001; Satoshi Goto; Takeshi Ikenaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization. - Yang Song 002; Zhenyu Liu 001; Takeshi Ikenaga; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

VLSI friendly edge gradient detection based multiple reference frames motion estimation optimization for H.264/AVC. - Zhenyu Liu 001; Yiqing Huang 002; Yang Song 002; Satoshi Goto; Takeshi Ikenaga (EUSIPCO, 2007)

Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. - Zhenyu Liu 001; Yiqing Huang 002; Yang Song 002; Satoshi Goto; Takeshi Ikenaga (ACM Great Lakes Symposium on VLSI, 2007)

VLSI Oriented Fast Multiple Reference Frame Motion Estimation Algorithm for H.264/AVC. - Zhenyu Liu 001; Lingfeng Li; Yang Song 002; Takeshi Ikenaga; Satoshi Goto (ICME, 2007)

Ultra Low-Complexity Fast Variable Block Size Motion Estimation Algorithm in H.264/AVC. - Yang Song 002; Zhenyu Liu 001; Takeshi Ikenaga; Satoshi Goto (ICME, 2007)

Enhanced Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation. - Yang Song 002; Zhenyu Liu 001; Takeshi Ikenaga; Satoshi Goto (ISCAS, 2007)

32-Parallel SAD Tree Hardwired Engine for Variable Block Size Motion Estimation in HDTV1080P Real-Time Encoding Application. - Zhenyu Liu 001; Yang Song 002; Ming Shao; Shen Li; Lingfeng Li; Satoshi Goto; Takeshi Ikenaga (SiPS, 2007)

H.264/AVC Fractional Motion Estimation Engine with Computation Reusing in HDTV1080P Real-Time Encoding Applications. - Yang Song 002; Ming Shao; Zhenyu Liu 001; Shen Li; Lingfeng Li; Takeshi Ikenaga; Satoshi Goto (SiPS, 2007)

Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation. - Ming Shao; Zhenyu Liu 001; Satoshi Goto; Takeshi Ikenaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Lossy Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation. - Yang Song 002; Zhenyu Liu 001; Takeshi Ikenaga; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations. - Yang Song 002; Zhenyu Liu 001; Takeshi Ikenaga; Satoshi Goto (IEICE Trans. Inf. Syst., 2007)

Optimization of Propagate Partial SAD and SAD tree motion estimation hardwired engine for H.264. - Zhenyu Liu 001; Satoshi Goto; Takeshi Ikenaga (ICCD, 2008)

Fast motion estimation for H.264/AVC using image edge features. - Zhenyu Liu 001; Satoshi Goto; Takeshi Ikenaga (ICME, 2008)

Hardware-oriented direction-based fast fractional motion estimation algorithm in H.264/AVC. - Yang Song 002; Yao Ma; Zhenyu Liu 001; Takeshi Ikenaga; Satoshi Goto (ICME, 2008)

Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC. - Yiqing Huang 002; Zhenyu Liu 001; Yang Song 002; Satoshi Goto; Takeshi Ikenaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Content-Aware Fast Motion Estimation for H.264/AVC. - Zhenyu Liu 001; Satoshi Goto; Takeshi Ikenaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Motion Feature and Hadamard Coefficient-Based Fast Multiple Reference Frame Motion Estimation for H.264. - Zhenyu Liu 001; Lingfeng Li; Yang Song 002; Shen Li; Satoshi Goto; Takeshi Ikenaga (IEEE Trans. Circuits Syst. Video Technol., 2008)

Hardware optimizations of variable block size Hadamard transform for H.264/AVC FRExt. - Zhenyu Liu 001; Dongsheng Wang 002; Takeshi Ikenaga (ICIP, 2009)

HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis. - Zhenyu Liu 001; Yang Song 002; Ming Shao; Shen Li; Lingfeng Li; Shunichi Ishiwata; Masaki Nakagawa; Satoshi Goto; Takeshi Ikenaga (IEEE J. Solid State Circuits, 2009)

Motion Estimation Optimization for H.264/AVC Using Source Image Edge Features. - Zhenyu Liu 001; Junwei Zhou; Satoshi Goto; Takeshi Ikenaga (IEEE Trans. Circuits Syst. Video Technol., 2009)

Architecture and Circuit Optimization of Hardwired Integer Motion Estimation Engine for H.264/AVC. - Zhenyu Liu 001; Dongsheng Wang 002; Takeshi Ikenaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

One-round renormalization based 2-bin/cycle H.264/AVC CABAC encoder. - Zhenyu Liu 001; Dongsheng Wang 002 (ICIP, 2011)

A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction. - Xi Zhang 008; Chongmin Li; Zhenyu Liu 001; Haixia Wang 001; Dongsheng Wang 002; Takeshi Ikenaga (IEICE Trans. Electron., 2011)

Register Length Analysis and VLSI Optimization of VBS Hadamard Transform in H.264/AVC. - Zhenyu Liu 001; Junwei Zhou; Dongsheng Wang 002; Takeshi Ikenaga (IEEE Trans. Circuits Syst. Video Technol., 2011)

Lagrangian Multiplier Optimization Using Markov Chain Based Rate and Piecewise Approximated Distortion Models. - Zhenyu Liu 001; Dongsheng Wang 002; Junwei Zhou; Takeshi Ikenaga (DCC, 2012)

Lagrangian multiplier optimization using correlations in residues. - Zhenyu Liu 001; Dongsheng Wang 002; Junwei Zhou; Takeshi Ikenaga (ICASSP, 2012)

A pixel-domain mode-mapping based SVC-to-AVC transcoder with coarse grain quality scalability. - Lei Sun 005; Zhenyu Liu 001; Takeshi Ikenaga (ICPR, 2012)

Wear-Resistant Hybrid Cache Architecture with Phase Change Memory. - Sanchuan Guo; Zhenyu Liu 001; Dongsheng Wang 002; Haixia Wang 001; Guohong Li (NAS, 2012)

A Videoconferencing-Oriented Hybrid-Domain H.264/SVC to H.264/AVC Spatial Transcoder. - Lei Sun 005; Zhenyu Liu 001; Takeshi Ikenaga (PCM, 2012)

Fast intra prediction for HEVC based on pixel gradient statistics and mode refinement. - Gaoxing Chen; Zhenyu Pei; Lei Sun 005; Zhenyu Liu 001; Takeshi Ikenaga (ChinaSIP, 2013)

41.7BN-pixels/s reconfigurable intra prediction architecture for HEVC 2560×1600 encoder. - Zhenyu Liu 001; Dongsheng Wang 002; Hongxiang Zhu; Xiaodong Huang (ICASSP, 2013)

Bayesian theory oriented Optimal Data-Provider Selection for CMP. - Guohong Li; Zhenyu Liu 001; Sanchuan Guo; Chongmin Li; Dongsheng Wang 002 (ICCD, 2013)

Fast prediction mode decision with hadamard transform based rate-distortion cost estimation for HEVC intra coding. - Jia Zhu; Zhenyu Liu 001; Dongsheng Wang 002; Qingrui Han; Yang Song 002 (ICIP, 2013)

Fast HEVC intra mode decision using matching edge detector and kernel density estimation alike histogram generation. - Guang Chen; Zhenyu Liu 001; Takeshi Ikenaga; Dongsheng Wang 002 (ISCAS, 2013)

Content-aware write reduction mechanism of phase-change RAM based Frame Store in H.264 Video codec system. - Sanchuan Guo; Zhenyu Liu 001; Guohong Li; Dongsheng Wang 002 (ISCAS, 2013)

A mode-mapping and optimized MV conjunction based MGS-scalable SVC to AVC IPPP transcoder. - Lei Sun 005; Zhenyu Liu 001; Takeshi Ikenaga (ISCAS, 2013)

Fully pipelined DCT/IDCT/Hadamard unified transform architecture for HEVC Codec. - Jia Zhu; Zhenyu Liu 001; Dongsheng Wang 002 (ISCAS, 2013)

Security Memory System for Mobile Device or Computer Against Memory Attacks. - Genxian Liu; Xi Zhang 008; Dongsheng Wang 002; Zhenyu Liu 001; Haixia Wang 001 (ISCTCS, 2013)

Fast mode and depth decision HEVC intra prediction based on edge detection and partitioning reconfiguration. - Gaoxing Chen; Lei Sun 005; Zhenyu Liu 001; Takeshi Ikenaga (ISPACS, 2013)

A Low-Complexity Quantization-Domain H.264/SVC to H.264/AVC Transcoder with Medium-Grain Quality Scalability. - Lei Sun 005; Zhenyu Liu 001; Takeshi Ikenaga (MMM (1), 2013)

Cluster Cache Monitor. - Guohong Li; Olivier Temam; Zhenyu Liu 001; Dongsheng Wang 002; Sanchuan Guo (SBAC-PAD, 2013)

Content-Aware Write Reduction Mechanism of 3D Stacked Phase-Change RAM Based Frame Store in H.264 Video Codec System. - Sanchuan Guo; Zhenyu Liu 001; Guohong Li; Takeshi Ikenaga; Dongsheng Wang 002 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Bayesian Theory Based Adaptive Proximity Data Accessing for CMP Caches. - Guohong Li; Zhenyu Liu 001; Sanchuan Guo; Dongsheng Wang 002 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A Drift-Constrained Frequency-Domain Ultra-Low-Delay H.264/SVC to H.264/AVC Transcoder with Medium-Grain Quality Scalability for Videoconferencing. - Lei Sun 005; Zhenyu Liu 001; Takeshi Ikenaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Low-Complexity Hybrid-Domain H.264/SVC to H.264/AVC Spatial Transcoding with Drift Compensation for Videoconferencing. - Lei Sun 005; Zhenyu Liu 001; Takeshi Ikenaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Improving Cache Partitioning Algorithms for Pseudo-LRU Policies. - Xi Zhang 008; Chuanyi Liu; Zhenyu Liu 001; Dongsheng Wang 002 (IEICE Trans. Inf. Syst., 2013)

Hardware oriented category pre-determination algorithm for SAO in HEVC. - Gaoxing Chen; Zhenyu Pei; Zhenyu Liu 001; Takeshi Ikenaga (APSIPA, 2014)

HDTV1080p HEVC Intra encoder with source texture based CU/PU mode pre-decision. - Jia Zhu; Zhenyu Liu 001; Dongsheng Wang 002; Qingrui Han; Yang Song 002 (ASP-DAC, 2014)

Linear Rate Estimation Model for HEVC RDO Using Binary Classification Based Regression. - Sanchuan Guo; Zhenyu Liu 001; Dongsheng Wang 002; Qingrui Han; Yang Song 002 (DCC, 2014)

Low complexity SAO in HEVC base on class combination, pre-decision and merge separation. - Gaoxing Chen; Zhenyu Pei; Zhenyu Liu 001; Takeshi Ikenaga (DSP, 2014)

Linear adaptive search range model for uni-prediction and motion analysis for bi-prediction in HEVC. - Longshan Du; Zhenyu Liu 001; Takeshi Ikenaga; Dongsheng Wang 002 (ICIP, 2014)

Binary classification based linear rate estimation model for HEVC RDO. - Zhenyu Liu 001; Sanchuan Guo; Dongsheng Wang 002 (ICIP, 2014)

Fast Mode and Depth Decision for HEVC Intra Prediction Based on Edge Detection and Partition Reconfiguration. - Gaoxing Chen; Lei Sun 005; Zhenyu Liu 001; Takeshi Ikenaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

A Mode Mapping and Optimized MV Conjunction Based H.264/SVC to H.264/AVC Transcoder with Medium-Grain Quality Scalability for Videoconferencing. - Lei Sun 005; Zhenyu Liu 001; Takeshi Ikenaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Pixel-grain prediction and K-order UEG-rice entropy coding oriented lossless frame memory compression for motion estimation in HEVC. - Xiaocong Lian; Zhenyu Liu 001; Wei Zhou 020; Zhemin Duan (ICIP, 2015)

VLSI friendly fast CU/PU mode decision for HEVC intra encoding: Leveraging convolution neural network. - Xianyu Yu; Zhenyu Liu 001; Junjie Liu; Yuan Gao; Dongsheng Wang 002 (ICIP, 2015)

Deblocking strength prediction based CTU-level SAO category determination in HEVC encoder. - Gaoxing Chen; Zhenyu Pei; Zhenyu Liu 001; Takeshi Ikenaga (VCIP, 2015)

An efficient interpolation filter VLSI architecture for HEVC standard. - Wei Zhou 020; Xin Zhou 001; Xiaocong Lian; Zhenyu Liu 001; Xiaoxiang Liu (EURASIP J. Adv. Signal Process., 2015)

Cluster Cache Monitor: Leveraging the Proximity Data in CMP. - Guohong Li; Olivier Temam; Zhenyu Liu 001; Sanchuan Guo; Dongsheng Wang 002 (Int. J. Parallel Program., 2015)

A low power lossy frame memory recompression algorithm. - Xin Zhou 001; Xiaocong Lian; Wei Zhou 020; Zhenyu Liu 001; Xiu Zhang (APSIPA, 2016)

Multi-feature based fast depth decision in HEVC inter prediction for VLSI implementation. - Gaoxing Chen; Zhenyu Liu 001; Tetsunori Kobayashi; Takeshi Ikenaga (CISP-BMEI, 2016)

CNN oriented fast HEVC intra CU mode decision. - Zhenyu Liu 001; Xianyu Yu; Shaolin Chen; Dongsheng Wang 002 (ISCAS, 2016)

Error models of finite word length arithmetic in CNN accelerator design. - Yuan Gao; Zhenyu Liu 001; Dongsheng Wang 002 (VCIP, 2016)

HEVC fast FME algorithm using IME RD-costs based error surface fitting scheme. - Yunpeng Li; Zhenyu Liu 001; Xiangyang Ji; Dongsheng Wang 002 (VCIP, 2016)

Hardware Oriented Enhanced Category Determination Based on CTU Boundary Deblocking Strength Prediction for SAO in HEVC Encoder. - Gaoxing Chen; Zhenyu Pei; Zhenyu Liu 001; Takeshi Ikenaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Lossless Frame Memory Compression Using Pixel-Grain Prediction and Dynamic Order Entropy Coding. - Xiaocong Lian; Zhenyu Liu 001; Wei Zhou 020; Zhemin Duan (IEEE Trans. Circuits Syst. Video Technol., 2016)

CU Partition Mode Decision for HEVC Hardwired Intra Encoder Using Convolution Neural Network. - Zhenyu Liu 001; Xianyu Yu; Yuan Gao; Shaolin Chen; Xiangyang Ji; Dongsheng Wang 002 (IEEE Trans. Image Process., 2016)

A High-Throughput and Multi-Parallel VLSI Architecture for HEVC Deblocking Filter. - Wei Zhou 020; Jingzhi Zhang; Xin Zhou 001; Zhenyu Liu 001; Xiaoxiang Liu (IEEE Trans. Multim., 2016)

A 200MHZ 202.4GFLOPS@10.8W VGG16 accelerator in Xilinx VX690T. - Chunsheng Mei; Zhenyu Liu 001; Yue Niu 001; Xiangyang Ji; Wei Zhou 020; Dongsheng Wang 002 (GlobalSIP, 2017)

Sensitivity-based acceleration and compression algorithm for convolution neural network. - Yue Niu 001; Zhenyu Liu 001; Chunsheng Mei; Xiangyang Ji; Wei Zhou 020; Dongsheng Wang 002 (GlobalSIP, 2017)

CNN oriented fast PU mode decision for HEVC hardwired intra encoder. - Nan Song; Zhenyu Liu 001; Xiangyang Ji; Dongsheng Wang 002 (GlobalSIP, 2017)

Coding sensitive based approximation algorithm for power efficient VBS-DCT VLSI design in HEVC hardwired Intra encoder. - Liangliang Chang; Zhenyu Liu 001; Xiangyang Ji; Dongsheng Wang 002 (ICIP, 2017)

Data-centric computation mode for convolution in deep neural networks. - Peiqi Wang 001; Zhenyu Liu 001; Haixia Wang 001; Dongsheng Wang 002 (IJCNN, 2017)

Computation Error Analysis of Block Floating Point Arithmetic Oriented Convolution Neural Network Accelerator Design. - Zhourui Song; Zhenyu Liu 001; Chunlu Wang; Dongsheng Wang 002 (CoRR, 2017)

Computation Error Analysis of Block Floating Point Arithmetic Oriented Convolution Neural Network Accelerator Design. - Zhourui Song; Zhenyu Liu 001; Dongsheng Wang 002 (AAAI, 2018)

Enhance the HEVC Fast Intra CU Mode Decision Based on Convolutional Neural Network by Corner Power Estimation. - Liangliang Chang; Zhenyu Liu 001; Libo Wang; Xiaobo Li (DCC, 2018)

Rate Control Optimization of X265 Using Information from Quarter-Resolution Pre-Motion-Estimation. - Zhenyu Liu 001; Libo Wang; Xiaobo Li (ICIP, 2018)

CNN Based CU Partition Mode Decision Algorithm for HEVC Inter Coding. - Yunpeng Li; Zhenyu Liu 001; Xiangyang Ji; Dongsheng Wang 002 (ICIP, 2018)

Parallel Content-Aware Adaptive Quantization-Oriented Lossy Frame Memory Recompression for HEVC. - Xiaocong Lian; Zhenyu Liu 001; Wei Zhou 020; Zhemin Duan (IEEE Trans. Circuits Syst. Video Technol., 2018)

A Block-Floating-Point Arithmetic Based FPGA Accelerator for Convolutional Neural Networks. - Heshan Zhang; Zhenyu Liu 001; Guanwen Zhang; Jiwu Dai; Xiaocong Lian; Wei Zhou 020; Xiangyang Ji (GlobalSIP, 2019)

Optimize x265 Rate Control: An Exploration of Lookahead in Frame Bit Allocation and Slice Type Decision. - Zhenyu Liu 001; Libo Wang; Xiaobo Li; Xiangyang Ji (IEEE Trans. Image Process., 2019)

High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic. - Xiaocong Lian; Zhenyu Liu 001; Zhourui Song; Jiwu Dai; Wei Zhou 020; Xiangyang Ji (IEEE Trans. Very Large Scale Integr. Syst., 2019)