Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvement. - Zhenyu Sun 001; Hai Li 001; Yiran Chen 001; Xiaobin Wang (ICCAD, 2010)

Multi retention level STT-RAM cache designs with a dynamic refresh scheme. - Zhenyu Sun 001; Xiuyuan Bi; Hai (Helen) Li; Weng-Fai Wong; Zhong-Liang Ong; Xiaochun Zhu; Wenqing Wu (MICRO, 2011)

Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches. - Xiuyuan Bi; Zhenyu Sun 001; Hai Li 001; Wenqing Wu (ICCAD, 2012)

Process variation aware data management for STT-RAM cache design. - Zhenyu Sun 001; Xiuyuan Bi; Hai Li 001 (ISLPED, 2012)

A dual-mode architecture for fast-switching STT-RAM. - Zhenyu Sun 001; Hai Li 001; Wenqing Wu (ISLPED, 2012)

Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder. - Zhenyu Sun 001; Xiang Chen 010; Yaojun Zhang; Hai Li 001; Yiran Chen 001 (ACM J. Emerg. Technol. Comput. Syst., 2012)

Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory. - Zhenyu Sun 001; Hai Li 001; Yiran Chen 001; Xiaobin Wang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Cross-layer racetrack memory design for ultra high density and low power consumption. - Zhenyu Sun 001; Wenqing Wu; Hai (Helen) Li (DAC, 2013)

A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. - Jianxing Wang; Yenni Tim; Weng-Fai Wong; Zhong-Liang Ong; Zhenyu Sun 001; Hai Li 001 (ASP-DAC, 2014)

Design exploration of racetrack lower-level caches. - Zhenyu Sun 001; Xiuyuan Bi; Alex K. Jones; Hai Li 001 (ISLPED, 2014)

STT-RAM Cache Hierarchy With Multiretention MTJ Designs. - Zhenyu Sun 001; Xiuyuan Bi; Hai Li 001; Weng-Fai Wong; Xiaochun Zhu (IEEE Trans. Very Large Scale Integr. Syst., 2014)

The evolutionary spintronic technologies and their usage in high performance computing. - Hai (Helen) Li; Xiuyuan Bi; Zhenyu Sun 001 (SoCC, 2015)

Read Performance: The Newest Barrier in Scaled STT-RAM. - Yaojun Zhang; Yong Li 009; Zhenyu Sun 001; Hai Li 001; Yiran Chen 001; Alex K. Jones (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Spintronic Memristor as Interface Between DNA and Solid State Devices. - Jianlei Yang 001; Zhenyu Sun 001; Xiaobin Wang; Yiran Chen 001; Hai Li 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Array Organization and Data Management Exploration in Racetrack Memory. - Zhenyu Sun 001; Xiuyuan Bi; Wenqing Wu; Sungjoo Yoo; Hai (Helen) Li (IEEE Trans. Computers, 2016)