Saidoyoki: Evaluating side-channel leakage in pre- and post-silicon setting. - Pantea Kiaei; Zhenyuan Liu 005; Ramazan Kaan Eren; Yuan Yao; Patrick Schaumont (IACR Cryptol. ePrint Arch., 2021)

Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment. - Pantea Kiaei; Zhenyuan Liu 005; Patrick Schaumont (ACM Great Lakes Symposium on VLSI, 2022)

Gate-Level Side-Channel Leakage Assessment with Architecture Correlation Analysis. - Pantea Kiaei; Yuan Yao; Zhenyuan Liu 005; Nicole Fern; Cees-Bart Breunesse; Jasper Van Woudenberg; Kate Gillis; Alex Dich; Peter Grossmann; Patrick Schaumont (CoRR, 2022)

FaultDetective Explainable to a Fault, from the Design Layout to the Software. - Zhenyuan Liu 005; Dillibabu Shanmugam; Patrick Schaumont (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024)

Gate-Level Side-Channel Leakage Ranking With Architecture Correlation Analysis. - Pantea Kiaei; Yuan Yao; Zhenyuan Liu 005; Nicole Fern; Cees-Bart Breunesse; Jasper Van Woudenberg; Kate Gillis; Alex Dich; Peter Grossmann; Patrick Schaumont (IEEE Trans. Emerg. Top. Comput., 2024)

μScan: Deep Learning Detection of Faulty Micro-architecture States and Patterns from Scan-Chain Data. - Dillibabu Shanmugam; Zhenyuan Liu 005; Andrew Malnicof; Patrick Schaumont (ACNS Workshops (1), 2025)

Telescope: Top-Down Hierarchical Pre-silicon Side-channel Leakage Assessment in System-on-Chip Design. - Zhenyuan Liu 005; Andrew Malnicof; Arna Roy; Patrick Schaumont (AsiaCCS, 2025)

GlitchGlück: Enabling Software Vulnerabilities through Guided Hardware Fault Injection. - Zhenyuan Liu 005; Dillibabu Shanmugam; Patrick Schaumont (WOOT, 2025)