When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies. - Zheyu Yan; Yiyu Shi 001; Wang Liao; Masanori Hashimoto; Xichuan Zhou; Cheng Zhuo (ASP-DAC, 2020)

Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks. - Lei Yang 018; Zheyu Yan; Meng Li 004; Hyoukjun Kwon; Liangzhen Lai; Tushar Krishna; Vikas Chandra; Weiwen Jiang; Yiyu Shi 001 (DAC, 2020)

Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search. - Zheyu Yan; Da-Cheng Juan; Xiaobo Sharon Hu; Yiyu Shi 001 (ASP-DAC, 2021)

Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators. - Weiwen Jiang; Qiuwen Lou; Zheyu Yan; Lei Yang 018; Jingtong Hu; Xiaobo Sharon Hu; Yiyu Shi 001 (IEEE Trans. Computers, 2021)

RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search. - Zheyu Yan; Weiwen Jiang; Xiaobo Sharon Hu; Yiyu Shi 001 (ASP-DAC, 2022)

SWIM: selective write-verify for computing-in-memory neural accelerators. - Zheyu Yan; Xiaobo Sharon Hu; Yiyu Shi 001 (DAC, 2022)

Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous? - Zheyu Yan; Xiaobo Sharon Hu; Yiyu Shi 001 (ICCAD, 2022)

A Semi-Decoupled Approach to Fast and Optimal Hardware-Software Co-Design of Neural Accelerators. - Bingqian Lu; Zheyu Yan; Yiyu Shi 001; Shaolei Ren (CoRR, 2022)

On the Reliability of Computing-in-Memory Accelerators for Deep Neural Networks. - Zheyu Yan; Xiaobo Sharon Hu; Yiyu Shi 001 (CoRR, 2022)

VisualNet: An End-to-End Human Visual System Inspired Framework to Reduce Inference Latency of Deep Neural Networks. - Tianchen Wang; Jiawei Zhang; Jinjun Xiong; Song Bian 001; Zheyu Yan; Meiping Huang; Jian Zhuang; Takashi Sato 001; Xiaowei Xu 004; Yiyu Shi 001 (IEEE Trans. Computers, 2022)

DASALS: Differentiable Architecture Search-Driven Approximate Logic Synthesis. - Xuan Wang; Zheyu Yan; Chang Meng; Yiyu Shi 001; Weikang Qian (ICCAD, 2023)

Improving Realistic Worst-Case Performance of NVCiM DNN Accelerators Through Training with Right-Censored Gaussian Noise. - Zheyu Yan; Yifan Qin; Wujie Wen; Xiaobo Sharon Hu; Yiyu Shi 001 (ICCAD, 2023)

On the Viability of Using LLMs for SW/HW Co-Design: An Example in Designing CiM DNN Accelerators. - Zheyu Yan; Yifan Qin; Xiaobo Sharon Hu; Yiyu Shi 001 (SOCC, 2023)

Negative Feedback Training: A Novel Concept to Improve Robustness of NVCiM DNN Accelerators. - Yifan Qin; Zheyu Yan; Wujie Wen; Xiaobo Sharon Hu; Yiyu Shi 001 (CoRR, 2023)

FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models : (Invited Paper). - Ruiyang Qin; Yuting Hu; Zheyu Yan; Jinjun Xiong; Ahmed Abbasi; Yiyu Shi 001 (ASPDAC, 2024)

Towards Fast Face Image Quality Assessment via Latent Diffusion Model. - Zheyu Yan; Weisong Zhao; Xiangyu Zhu 001; Li Gao; Xiaoyu Zhang 002; Zhen Lei 001 (CCBR (1), 2024)

Special Session: Sustainable Deployment of Deep Neural Networks on Non-Volatile Compute-in-Memory Accelerators. - Yifan Qin; Zheyu Yan; Wujie Wen; Xiaobo Sharon Hu; Yiyu Shi 001 (CODES+ISSS, 2024)

TSB: Tiny Shared Block for Efficient DNN Deployment on NVCIM Accelerators. - Yifan Qin; Zheyu Yan; Zixuan Pan; Wujie Wen; Xiaobo Sharon Hu; Yiyu Shi 001 (ICCAD, 2024)

Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory Architectures. - Ruiyang Qin; Zheyu Yan; Dewen Zeng; Zhenge Jia; Dancheng Liu; Jianbo Liu; Ahmed Abbasi; Zhi Zheng; Ningyuan Cao; Kai Ni 004; Jinjun Xiong; Yiyu Shi 001 (ICCAD, 2024)

FRCSyn Challenge at WACV 2024: Face Recognition Challenge in the Era of Synthetic Data. - Pietro Melzi; Ruben Tolosana; Rubén Vera-Rodríguez; Minchul Kim; Christian Rathgeb; Xiaoming Liu 002; Ivan DeAndres-Tame; Aythami Morales; Julian Fiérrez; Javier Ortega-Garcia; Weisong Zhao; Xiangyu Zhu 001; et al. (WACV (Workshops), 2024)

FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models. - Ruiyang Qin; Yuting Hu; Zheyu Yan; Jinjun Xiong; Ahmed Abbasi; Yiyu Shi 001 (CoRR, 2024)

Robust Implementation of Retrieval-Augmented Generation on Edge-based Computing-in-Memory Architectures. - Ruiyang Qin; Zheyu Yan; Dewen Zeng; Zhenge Jia; Dancheng Liu; Jianbo Liu; Zhi Zheng; Ningyuan Cao; Kai Ni 004; Jinjun Xiong; Yiyu Shi 001 (CoRR, 2024)

Empirical Guidelines for Deploying LLMs onto Resource-constrained Edge Devices. - Ruiyang Qin; Dancheng Liu; Zheyu Yan; Zhaoxuan Tan; Zixuan Pan; Zhenge Jia; Meng Jiang 001; Ahmed Abbasi; Jinjun Xiong; Yiyu Shi 001 (CoRR, 2024)

Rethinking Medical Anomaly Detection in Brain MRI: An Image Quality Assessment Perspective. - Zixuan Pan; Jun Xia 003; Zheyu Yan; Guoyue Xu; Yawen Wu; Zhenge Jia; Jianxu Chen 001; Yiyu Shi 001 (CoRR, 2024)

Tiny-Align: Bridging Automatic Speech Recognition and Large Language Model on the Edge. - Ruiyang Qin; Dancheng Liu; Gelei Xu; Zheyu Yan; Chenhui Xu; Yuting Hu; X. Sharon Hu; Jinjun Xiong; Yiyu Shi 001 (CoRR, 2024)

FRCSyn-onGoing: Benchmarking and comprehensive evaluation of real and synthetic data to improve face recognition systems. - Pietro Melzi; Ruben Tolosana; Rubén Vera-Rodríguez; Minchul Kim; Christian Rathgeb; Xiaoming Liu 002; Ivan DeAndres-Tame; Aythami Morales; Julian Fiérrez; Javier Ortega-Garcia; Weisong Zhao; Xiangyu Zhu 001; et al. (Inf. Fusion, 2024)

U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators. - Zheyu Yan; Xiaobo Sharon Hu; Yiyu Shi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Compute-in-Memory-Based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections. - Zheyu Yan; Xiaobo Sharon Hu; Yiyu Shi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Personalized Meta-Federated Learning for IoT-Enabled Health Monitoring. - Zhenge Jia; Tianren Zhou; Zheyu Yan; Jingtong Hu; Yiyu Shi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Invited Paper: Boosting Standard Cell Library Characterization with Machine Learning. - Zhengrui Chen; Chengjun Guo; Zixuan Song; Guozhu Feng; Shizhang Wang; Li Zhang 021; Xunzhao Yin; Zhenhua Wu; Zheyu Yan; Cheng Zhuo (ASP-DAC, 2025)

A 10.60 μW 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection. - Yifan Qin; Zhenge Jia; Zheyu Yan; Jay Mok; Manto Yung; Yu Liu 007; Xuejiao Liu; Wujie Wen; Luhong Liang; Kwang-Ting (Tim) Cheng; Xiaobo Sharon Hu; Yiyu Shi 001 (ASP-DAC, 2025)

Algorithm-Hardware Co-Design of a Unified Accelerator for Non-Linear Functions in Transformers. - Haonan Du; Chenyi Wen; Zhengrui Chen; Li Zhang 021; Qi Sun 002; Zheyu Yan; Cheng Zhuo (DATE, 2025)

NVCiM-PT: An NVCiM-Assisted Prompt Tuning Framework for Edge LLMs. - Ruiyang Qin; Pengyu Ren; Zheyu Yan; Liu Liu; Dancheng Liu; Amir Nassereldine; Jinjun Xiong; Kai Ni 004; X. Sharon Hu; Yiyu Shi 001 (DATE, 2025)

ANAS: Software-hardware co-design of approximate neural network accelerators via neural architecture search. - Ying Wu; Zheyu Yan; Xunzhao Yin; Lenian He; Cheng Zhuo (Integr., 2025)

CSA-CiM: Enhancing Multifunctional Computing-in-Memory With Configurable Sense Amplifiers. - Yuxiao Jiang; Kai Ni 004; Thomas Kämpfe; Cheng Zhuo; Zheyu Yan; Xunzhao Yin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

FactorHD: A Hyperdimensional Computing Model for Multi-Object Multi-Class Representation and Factorization. - Yifei Zhou; Xuchu Huang; Chenyu Ni; Min Zhou; Zheyu Yan; Xunzhao Yin; Cheng Zhuo (CoRR, 2025)

SenHDC: A 3-D NAND Flash-Based Processing-in-Sensor Hyperdimensional Computing Architecture. - Xuchu Huang; Qingrong Huang; Zeyu Yang; Min Zhou; Zheyu Yan; Cheng Zhuo; Xunzhao Yin (IEEE Trans. Very Large Scale Integr. Syst., 2025)