An Ultra Low-power Current-mode Sense Amplifier for Sram Applications. - Zhi-Hui Kong; Kiat Seng Yeo; Chip-Hong Chang (J. Circuits Syst. Comput., 2005)

A full current-mode sense amplifier for low-power SRAM applications. - Anh-Tuan Do; Jeremy Yung Shern Low; Zhi-Hui Kong; Kiat Seng Yeo; Joshua Yung Low Yung Lih (APCCAS, 2008)

Body-bootstrapped-buffer circuit for CMOS static power reduction. - Liang-Yu Loy; Weija Zhang; Zhi-Hui Kong; Wang Ling Goh; Kiat Seng Yeo (APCCAS, 2008)

Spicesoft: Automated Tool for Sensitivity Analysis, Performance Analysis, and Inverse Performance Analysis of Digital Circuits. - Kiat Seng Yeo; Zhi-Hui Kong (J. Circuits Syst. Comput., 2008)

Integrated Circuit Design Research Ranking for Worldwide Universities. - Kiat Seng Yeo; Zhi-Hui Kong; Nukala Nishant; Haitao Fu; Wei Zeng (J. Circuits Syst. Comput., 2008)

Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing. - Anh-Tuan Do; Zhi-Hui Kong; Kiat Seng Yeo (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Low IR drop and low power parallel CAM design using gated power transistor technique. - Anh-Tuan Do; Shoushun Chen; Zhi-Hui Kong; Kiat Seng Yeo (APCCAS, 2010)

An 8T SRAM cell with column-based dynamic supply voltage for bit-interleaving. - Anh-Tuan Do; Kiat Seng Yeo; Jeremy Yung Shern Low; Joshua Yung Lih Low; Zhi-Hui Kong (APCCAS, 2010)

A 16Kb 10T-SRAM with 4x read-power reduction. - Zhi-Hui Kong; Anh-Tuan Do (ISCAS, 2010)

Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier. - Anh-Tuan Do; Zhi-Hui Kong; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing. - Ning Zhu; Wang Ling Goh; Weija Zhang; Kiat Seng Yeo; Zhi-Hui Kong (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A new match line sensing technique in Content Addressable Memory. - Xiaoliang Tan; Anh-Tuan Do; Shoushun Chen; Kiat Seng Yeo; Zhi-Hui Kong (COOL Chips, 2011)

A comparative study of state-of-the-art low-power CAM match-line sense amplifier designs. - Anh-Tuan Do; Xiaoliang Tan; Shoushun Chen; Zhi-Hui Kong; Kiat Seng Yeo (ACM Great Lakes Symposium on VLSI, 2011)

A low-power CAM with efficient power and delay trade-off. - Anh-Tuan Do; Shoushun Chen; Zhi-Hui Kong; Kiat Seng Yeo (ISCAS, 2011)

Impacts of NBTI/PBTI on SRAM VMIN and design techniques for SRAM VMIN improvement. - Tony Tae-Hyoung Kim; Zhi-Hui Kong (ISOCC, 2011)

An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS. - Anh-Tuan Do; Jeremy Yung Shern Low; Joshua Yung Lih Low; Zhi-Hui Kong; Xiaoliang Tan; Kiat Seng Yeo (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM. - Anh-Tuan Do; Zhi-Hui Kong; Kiat Seng Yeo; Jeremy Yung Shern Low (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Recent progress in silicon-based millimeter-wave power amplifier. - Jiang An Han; Zhi-Hui Kong; Kaixue Ma; Kiat Seng Yeo (APCCAS, 2012)

CMOS-MEMS capacitive sensors for intra-cranial pressure monitoring: Sensor fabrication & system design. - Arup K. George; Wai Pan Chan; Margarita Sofia Narducci; Zhi-Hui Kong; Minkyu Je (ISOCC, 2012)

NBTI/PBTI-aware wordline voltage control with no boosted supply for stability improvement of half-selected SRAM cells. - Zhao Chuan Lee; Kim Ming Ho; Zhi-Hui Kong; Tony T. Kim (ISOCC, 2012)

A current-mode stimulator circuit with two-step charge balancing background calibration. - Anh-Tuan Do; Yung Sern Tan; Gordon M. Xiong; Cleo Choong; Zhi-Hui Kong; Kiat Seng Yeo (ISCAS, 2013)

PCKGen: A Phase Change Memory based cryptographic key generator. - Le Zhang 001; Zhi-Hui Kong; Chip-Hong Chang (ISCAS, 2013)

NBTI/PBTI-Aware WWL Voltage Control for Half-Selected Cell Stability Improvement. - Zhao Chuan Lee; Kam Chew Leong; Zhi-Hui Kong; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing. - Anh-Tuan Do; Shoushun Chen; Zhi-Hui Kong; Kiat Seng Yeo (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Leakage-resilient memory-based physical unclonable function using phase change material. - Le Zhang 001; Chip-Hong Chang; Alessandro Cabrini; Guido Torelli; Zhi-Hui Kong (ICCST, 2014)

Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM. - Le Zhang 001; Xuanyao Fong; Chip-Hong Chang; Zhi-Hui Kong; Kaushik Roy 001 (ISCAS, 2014)

A Monolithically Integrated Pressure/Oxygen/Temperature Sensing SoC for Multimodality Intracranial Neuromonitoring. - Wai Pan Chan; Margarita Narducci; Yuan Gao 011; Ming-Yuan Cheng; Jia Hao Cheong; Arup K. George; Daw Don Cheam; Siew Chong Leong; Maria Ramona B. Damalerio; Ruiqi Lim; Ming-Ling Tsai; Abdur R. A. Rahman; et al. (IEEE J. Solid State Circuits, 2014)

Exploiting Process Variations and Programming Sensitivity of Phase Change Memory for Reconfigurable Physical Unclonable Functions. - Le Zhang 001; Zhi-Hui Kong; Chip-Hong Chang; Alessandro Cabrini; Guido Torelli (IEEE Trans. Inf. Forensics Secur., 2014)

A 57 to 66 GHz novel six-port correlator. - Peng Siew Chew; Kiat Seng Yeo; Kaixue Ma; Zhi-Hui Kong (ASICON, 2015)

Statistical analysis and design of 6T SRAM cell for physical unclonable function with dual application modes. - Le Zhang 001; Chip-Hong Chang; Zhi-Hui Kong; Chao Qun Liu (ISCAS, 2015)

Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator. - Le Zhang 001; Xuanyao Fong; Chip-Hong Chang; Zhi-Hui Kong; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Highly Reliable Spin-Transfer Torque Magnetic RAM-Based Physical Unclonable Function With Multi-Response-Bits Per Cell. - Le Zhang 001; Xuanyao Fong; Chip-Hong Chang; Zhi-Hui Kong; Kaushik Roy 001 (IEEE Trans. Inf. Forensics Secur., 2015)

An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI. - Zhao Chuan Lee; M. Sultan M. Siddiqui; Zhi-Hui Kong; Tony Tae-Hyoung Kim (ESSCIRC, 2016)

A High-Efficiency 6.78-MHz Full Active Rectifier With Adaptive Time Delay Control for Wireless Power Transmission. - Xiaoyin Bai; Zhi-Hui Kong; Liter Siek (IEEE Trans. Very Large Scale Integr. Syst., 2017)

An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Operation in 28-nm FDSOI. - Zhao Chuan Lee; M. Sultan M. Siddiqui; Zhi-Hui Kong; Tony Tae-Hyoung Kim (IEEE J. Solid State Circuits, 2019)

Towards Safe and Efficient Analog Circuit Design: Active Learning for Feasibility Region Exploration. - Sezin Kircali Ata; Zhi-Hui Kong; Anusha James; Lile Cai; Kiat Seng Yeo; Khin Mi Mi Aung; Chuan Sheng Foo; Ashish James (APCCAS, 2024)

The Initialization Factor: Understanding its Impact on Active Learning for Analog Circuit Design. - Sezin Kircali Ata; Zhi-Hui Kong; Anusha James; Lile Cai; Kiat Seng Yeo; Khin Mi Mi Aung; Chuan Sheng Foo; Ashish James (ISCAS, 2024)