A 4-GS/s 8-bit two-channel time-interleaved folding and interpolating ADC. - Fan Jiang; DanYu Wu; Lei Zhou 014; Jin Wu; Zhi Jin 003; Xinyu Liu 004 (Sci. China Inf. Sci., 2014)

A 35-GHz Bandwidth 30 GSa/s InP Track-and-Hold Amplifier Using Enhanced fT-Doubler Technique. - Wenxiang Zhen; Luning Xiao; Shurui Cao; Yongbo Su; Zhi Jin 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 100 Gb/s PAM4 receiver analog front-end with 33.1-dB boost in 28-nm CMOS process. - Qiuyue Zhang; Xuqiang Zheng; Fangxu Lv; Wenxiang Zhen; Mingche Lai; Zhi Jin 003; Xinyu Liu 004 (IEICE Electron. Express, 2025)

A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS. - Hua Xu; Mingche Lai; Xuqiang Zheng; Zedong Wang; Jiang Xu; Sai Li; Fangxu Lv; Min Liu; Weijie Li; Zhanhao Wen; Xuan Guo; Xinhua Wang; et al. (IEEE J. Solid State Circuits, 2025)