A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference. - Wang Ye; Linfang Wang; Zhidao Zhou; Junjie An; Weizeng Li; Hanghang Gao; Zhi Li 062; Jinshan Yue; Hongyang Hu; Xiaoxin Xu; Jianguo Yang; Jing Liu 035; et al. (IEEE J. Solid State Circuits, 2023)

A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators. - Weizeng Li; Linfang Wang; Zhi Li 062; Wang Ye; Zhidao Zhou; Haiyang Zhou; Hanghang Gao; Jinshan Yue; Hongyang Hu; Fengman Liu; Qing Luo; Chunmeng Dou (ISCAS, 2024)

34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process. - Linfang Wang; Weizeng Li; Zhidao Zhou; Hanghang Gao; Zhi Li 062; Wang Ye; Hongyang Hu; Jing Liu 035; Jinshan Yue; Jianguo Yang; Qing Luo; Chunmeng Dou; et al. (ISSCC, 2024)

First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (5000s). - Menggan Liu; Zhi Li 062; Wendong Lu; Kaifei Chen; Jiebin Niu; Fuxi Liao; Zijing Wu; Congyan Lu; Weizeng Li; Di Geng; Nianduan Lu; Chunmeng Dou; et al. (VLSI Technology and Circuits, 2024)

Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge. - Junjie An; Zhidao Zhou; Linfang Wang; Wang Ye; Weizeng Li; Hanghang Gao; Zhi Li 062; Jinghui Tian; Yan Wang; Hongyang Hu; Jinshan Yue; Lingyan Fan; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2024)

SHMT: An SRAM and HBM Hybrid Computing-in-Memory Architecture With Optimized KV Cache for Multimodal Transformer. - Xiangqu Fu; Jinshan Yue; Muhammad Faizan; Zhi Li 062; Qiang Huo; Feng Zhang 014 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree. - Wang Ye; Hanghang Gao; Zhidao Zhou; Linfang Wang; Weizeng Li; Zhi Li 062; Jinshan Yue; Xiaoxin Xu; Jianguo Yang; Hongyang Hu; Chunmeng Dou (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications. - Jun Wang; Shengzhe Yan; Xiangqu Fu; Zhihang Qian; Zhi Li 062; Zeyu Guo 002; Zhuoyu Dai; Zhaori Cong; Chunmeng Dou; Feng Zhang 014; Jinshan Yue; Dashan Shang (IEEE Trans. Very Large Scale Integr. Syst., 2025)