Zhibin Yu

According to our database1, Zhibin Yu authored at least 34 papers between 2008 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
MIA: Metric Importance Analysis for Big Data Workload Characterization.
IEEE Trans. Parallel Distrib. Syst., 2018

QIG: Quantifying the Importance and Interaction of GPGPU Architecture Parameters.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Configuring in-memory cluster computing using random forest.
Future Generation Comp. Syst., 2018

The Elasticity and Plasticity in Semi-Containerized Co-locating Cloud Workload: a View from Alibaba Trace.
Proceedings of the ACM Symposium on Cloud Computing, 2018

2017
ATH: Auto-Tuning HBase's Configuration via Ensemble Learning.
IEEE Access, 2017

MEST: A Model-Driven Efficient Searching Approach for MapReduce Self-Tuning.
IEEE Access, 2017

BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

An Experimental Comparison Between Genetic Algorithm and Particle Swarm Optimization in Spark Performance Tuning.
Proceedings of the first Workshop on Emerging Technologies for software-defined and reconfigurable hardware-accelerated Cloud Datacenters, 2017

POSTER: BACM: Barrier-Aware Cache Management for Irregular Memory-Intensive GPGPU Workloads.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
RFHOC: A Random-Forest Approach to Auto-Tuning Hadoop's Configuration.
IEEE Trans. Parallel Distrib. Syst., 2016

ShenZhen transportation system (SZTS): a novel big data benchmark suite.
The Journal of Supercomputing, 2016

Two-Level Hybrid Sampled Simulation of Multithreaded Applications.
TACO, 2016

QIM: Quantifying Hyperparameter Importance for Deep Learning.
Proceedings of the Network and Parallel Computing, 2016

Barrier-Aware Warp Scheduling for Throughput Processors.
Proceedings of the 2016 International Conference on Supercomputing, 2016

Thread Similarity Matrix: Visualizing Branch Divergence in GPGPU Programs.
Proceedings of the 45th International Conference on Parallel Processing, 2016

Performance Modeling for Spark Using SVM.
Proceedings of the 7th International Conference on Cloud Computing and Big Data, 2016

2015
GPGPU-MiniBench: Accelerating GPGPU Micro-Architecture Simulation.
IEEE Trans. Computers, 2015

SZTS: A Novel Big Data Transportation System Benchmark Suite.
Proceedings of the 44th International Conference on Parallel Processing, 2015

Shorter On-Line Warmup for Sampled Simulation of Multi-threaded Applications.
Proceedings of the 44th International Conference on Parallel Processing, 2015

2014
A comparative study on resource allocation and energy efficient job scheduling strategies in large-scale parallel computing systems.
Cluster Computing, 2014

2013
PCantorSim: Accelerating parallel architecture simulation through fractal-based sampling.
TACO, 2013

Accelerating GPGPU architecture simulation.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2013

Application-Aware Workload Consolidation to Minimize Both Energy Consumption and Network Load in Cloud Environments.
Proceedings of the 42nd International Conference on Parallel Processing, 2013

A characterization of big data benchmarks.
Proceedings of the 2013 IEEE International Conference on Big Data, 2013

2012
FractalMRC: Online Cache Miss Rate Curve Prediction on Commodity Systems.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

2011
MT-BTRIMER: A master-slave multi-threaded dynamic binary translator.
Comput. Syst. Sci. Eng., 2011

Hierarchically characterizing CUDA program behavior.
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011

2010
CantorSim: Simplifying Acceleration of Micro-architecture Simulations.
Proceedings of the MASCOTS 2010, 2010

MT-BTRIMER: A Master-Slave Multi-threaded Dynamic Binary Translator.
Proceedings of the Fifth International Conference on Frontier of Computer Science and Technology, 2010

System-level max power (SYMPO): a systematic approach for escalating system-level power consumption using synthetic benchmarks.
Proceedings of the 19th International Conference on Parallel Architecture and Compilation Techniques, 2010

2009
Simple and fast micro-architecture simulation: a trisection cantor fractal approach.
SIGMETRICS Performance Evaluation Review, 2009

TSS: Applying two-stage sampling in micro-architecture simulations.
Proceedings of the 17th Annual Meeting of the IEEE/ACM International Symposium on Modelling, 2009

2008
Identifying Classes via Cognitive Approach in Object-Oriented System.
Proceedings of the PACIIA 2008, 2008

An Evaluation of Two-Stage Systematic Sampling in Micro-Architecture Simulation.
Proceedings of the Third ChinaGrid Annual Conference, ChinaGrid 2008, Dunhuang, Gansu, 2008


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