An energy-efficient heterogeneous dual-core processor for Internet of Things. - Zhibo Wang 004; Yongpan Liu; Yinan Sun; Yang Li; Daming Zhang; Huazhong Yang (ISCAS, 2015)

Design exploration of inrush current aware controller for nonvolatile processor. - Yongpan Liu; Fang Su; Zhibo Wang 004; Huazhong Yang (NVMSA, 2015)

Multistage Function Speculation Adders. - Yinan Sun; Yongpan Liu; Zhibo Wang 004; Huazhong Yang (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic. - Yongpan Liu; Zhibo Wang 004; Albert Lee; Fang Su; Chieh-Pu Lo; Zhe Yuan; Chien-Chen Lin; Qi Wei 001; Yu Wang 002; Ya-Chin King; Chrong Jung Lin; Pedram Khalili; et al. (ISSCC, 2016)

A compare-and-select error tolerant scheme for nonvolatile processors. - Zhibo Wang 004; Rui Hua; Yongpan Liu; Huazhong Yang (NANOARCH, 2016)

Design of nonvolatile processors and applications. - Fang Su; Zhibo Wang 004; Jinyang Li 002; Meng-Fan Chang; Yongpan Liu (VLSI-SoC, 2016)

A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors. - Albert Lee; Chieh-Pu Lo; Chien-Chen Lin; Wei-Hao Chen; Kuo-Hsiang Hsu; Zhibo Wang 004; Fang Su; Zhe Yuan; Qi Wei 001; Ya-Chin King; Chrong Jung Lin; Hochul Lee; et al. (IEEE J. Solid State Circuits, 2017)

A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed. - Zhibo Wang 004; Yongpan Liu; Albert Lee; Fang Su; Chieh-Pu Lo; Zhe Yuan; Jinyang Li 002; Chien-Chen Lin; Wei-Hao Chen; Hsiao-Yun Chiu; Wei-En Lin; Ya-Chin King; et al. (IEEE J. Solid State Circuits, 2017)

NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing. - Kaisheng Ma; Xueqing Li 002; Mahmut Taylan Kandemir; Jack Sampson; Vijaykrishnan Narayanan; Jinyang Li 002; Tongda Wu; Zhibo Wang 004; Yongpan Liu; Yuan Xie 001 (ASPLOS, 2018)

A 2-GHz Direct Digital Frequency Synthesizer Based on LUT and Rotation. - Yixiong Yang; Zhibo Wang 004; Pei Yang; Meng-Fan Chang; Mon-Shu Ho; Huazhong Yang; Yongpan Liu (ISCAS, 2018)

Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers. - Zhe Yuan; Jinshan Yue; Huanrui Yang; Zhibo Wang 004; Jinyang Li 002; Yixiong Yang; Qingwei Guo; Xueqing Li 002; Meng-Fan Chang; Huazhong Yang; Yongpan Liu (VLSI Circuits, 2018)

AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip. - Jinshan Yue; Yongpan Liu; Fang Su; Shuangchen Li; Zhe Yuan; Zhibo Wang 004; Wenyu Sun; Xueqing Li 002; Huazhong Yang (ASP-DAC, 2019)

A Sparse-Adaptive CNN Processor with Area/Performance balanced N-Way Set-Associate PE Arrays Assisted by a Collision-Aware Scheduler. - Zhe Yuan; Jingyu Wang 004; Yixiong Yang; Jinshan Yue; Zhibo Wang 004; Xiaoyu Feng; Yanzhi Wang; Xueqing Li 002; Huazhong Yang; Yongpan Liu (A-SSCC, 2019)

A 65nm 0.39-to-140.3TOPS/W 1-to-12b Unified Neural Network Processor Using Block-Circulant-Enabled Transpose-Domain Acceleration with 8.1 × Higher TOPS/mm2and 6T HBST-TRAM-Based 2D Data-Reuse Architecture. - Jinshan Yue; Ruoyang Liu; Wenyu Sun; Zhe Yuan; Zhibo Wang 004; Yung-Ning Tu; Yi-Ju Chen; Ao Ren; Yanzhi Wang; Meng-Fan Chang; Xueqing Li 002; Huazhong Yang; et al. (ISSCC, 2019)

A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System. - Yongpan Liu; Fang Su; Yixiong Yang; Zhibo Wang 004; Yiqun Wang; Zewei Li; Xueqing Li 002; Ryuji Yoshimura; Takashi Naiki; Takashi Tsuwa; Takahiko Saito; Zhongjun Wang; et al. (IEEE J. Solid State Circuits, 2019)

A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation. - Yixiong Yang; Xin Shi; Fang Su; Zhibo Wang 004; Pei Yang; Huazhong Yang; Yongpan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 3.77TOPS/W Convolutional Neural Network Processor With Priority-Driven Kernel Optimization. - Jinshan Yue; Yongpan Liu; Zhe Yuan; Zhibo Wang 004; Qingwei Guo; Jinyang Li 002; Chengmo Yang; Huazhong Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2019)