A 0.012mm2 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply. - Zhicheng Dong 002; Shubin Liu; Xiaoteng Zhao; Baotian Hao; Hongzhi Liang; Haolin Han; Menghao Wang; Weijie Han; Zhangming Zhu (CICC, 2023)

A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage. - Yi Shen 007; Shubin Liu; Yue Cao; Haolin Han; Hongzhi Liang; Zhicheng Dong 002; Dengquan Li; Ruixue Ding; Zhangming Zhu (CICC, 2023)

A 0.0006-mm2 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS. - Zhicheng Dong 002; Xiaoteng Zhao; Zekai Yang; Xianting Su; Haolin Han; Feng Bu; Rong Zhou; Depeng Sun; Yong Chen 005; Shubin Liu; Ruixue Ding; Zhangming Zhu (A-SSCC, 2024)

A 0.9-V Supply Up to 21.5-dB Boost Gain Analog Front-End with T-coilloaded CTLE and VGA in 28-nm CMOS for 112-Gb/s PAM-4 Medium-Reach Receivers. - Miao Zhang; Xianting Su; Zekai Yang; Zhicheng Dong 002; Weitan Huang; Menghao Wang; Yukui Yu; Xiaoteng Zhao; Shubin Liu; Zhangming Zhu (ICTA, 2024)

A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm2 Area. - Zhicheng Dong 002; Xiaoteng Zhao; Weitan Huang; Yuan Gao; Depeng Sun; Shubin Liu; Lihong Yang; Zhangming Zhu (ISCAS, 2024)

A 0.08%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With VGS-Ratio-Based Compensation Using One-Type-Only Resistor. - Zhicheng Dong 002; Shubin Liu; Xiaoteng Zhao; Baotian Hao; Xianting Su; Hongzhi Liang; Menghao Wang; Zhangming Zhu (IEEE J. Solid State Circuits, 2024)

A Reference-Less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 63.64Gb/s/µs Acquisition Speed. - Xiaoteng Zhao; Yuhao Zhang; Hao Chang; Yilong Dong; Chenxi Han; Zekai Yang; Zhicheng Dong 002; Rong Zhou; Shubin Liu; Zhangming Zhu (ISSCC, 2025)

A 7-bit 8 GHz phase interpolator with eight-phase output using a linear weighting scheme using only 50 % interpolation units. - Jie Liu; Xianting Su; Zekai Yang; Zhicheng Dong 002; Chenxi Han; Xiaoteng Zhao; Shubin Liu (Microelectron. J., 2025)

Load-driven inductive peaking design for broad band continuous-time linear equalizer. - Miao Zhang; Ruidong Li; Xiaoteng Zhao; Xianting Su; Zhicheng Dong 002; Zekai Yang; Hongyu Su; Hongzhi Liang; Yukui Yu; Shubin Liu (Microelectron. J., 2025)

A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage. - Yi Shen 007; Shubin Liu; Yue Cao; Haolin Han; Hongzhi Liang; Zhicheng Dong 002; Dengquan Li; Ruixue Ding; Zhangming Zhu (IEEE J. Solid State Circuits, 2025)

A 0.4-V 500-kHz FLL With Reused TDA-Based Calibration and OTA-Accelerated Technique in 65-nm CMOS for Sleep Timer. - Linwei Wang; Rong Zhou; Jianhang Yang; Zhen Li; Zhicheng Dong 002; Shubin Liu; Zhangming Zhu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)