A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. - Zhao Zhang 010; Zhichun Zhu; Xiaodong Zhang 001 (MICRO, 2000)

Memory Hierarchy Considerations for Cost-Effective Cluster Computing. - Xing Du; Xiaodong Zhang 001; Zhichun Zhu (IEEE Trans. Computers, 2000)

Breaking Address Mapping Symmetry at Multi-levels of Memory Heirarchy to Reduce DRAM Row-buffer Conflicts. - Zhao Zhang 010; Zhichun Zhu; Xiaodong Zhang 001 (J. Instr. Level Parallelism, 2001)

Cached DRAM for ILP Processor Memory Access Latency Reduction. - Zhao Zhang 010; Zhichun Zhu; Xiaodong Zhang 001 (IEEE Micro, 2001)

Fine-Grain Priority Scheduling on Multi-Channel Memory Systems. - Zhichun Zhu; Zhao Zhang 010; Xiaodong Zhang 001 (HPCA, 2002)

Access-Mode Predictions for Low-Power Cache Design. - Zhichun Zhu; Xiaodong Zhang 001 (IEEE Micro, 2002)

Design and Optimization of Large Size and Low Overhead Off-Chip Caches. - Zhao Zhang 010; Zhichun Zhu; Xiaodong Zhang 001 (IEEE Trans. Computers, 2004)

A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. - Zhichun Zhu; Zhao Zhang 010 (HPCA, 2005)

Look-Ahead Architecture Adaptation to Reduce Processor Power Consumption. - Zhichun Zhu; Xiaodong Zhang 001 (IEEE Micro, 2005)

Thermal modeling and management of DRAM memory systems. - Jiang Lin; Hongzhong Zheng; Zhichun Zhu; Howard David; Zhao Zhang 010 (ISCA, 2007)

DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. - Jiang Lin; Hongzhong Zheng; Zhichun Zhu; Zhao Zhang 010; Howard David (ISPASS, 2007)

Memory Access Scheduling Schemes for Systems with Multi-Core Processors. - Hongzhong Zheng; Jiang Lin; Zhao Zhang 010; Zhichun Zhu (ICPP, 2008)

Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. - Hongzhong Zheng; Jiang Lin; Zhao Zhang 010; Eugene Gorbatov; Howard David; Zhichun Zhu (MICRO, 2008)

Software thermal management of dram memory for multicore systems. - Jiang Lin; Hongzhong Zheng; Zhichun Zhu; Eugene Gorbatov; Howard David; Zhao Zhang 010 (SIGMETRICS, 2008)

Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. - Hongzhong Zheng; Jiang Lin; Zhao Zhang 010; Zhichun Zhu (ISCA, 2009)

Heterogeneous Mini-rank: Adaptive, Power-Efficient Memory Architecture. - Kun Fang 005; Hongzhong Zheng; Zhichun Zhu (ICPP, 2010)

Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors. - Hongzhong Zheng; Zhichun Zhu (IEEE Trans. Computers, 2010)

Memory Architecture for Integrating Emerging Memory Technologies. - Kun Fang 005; Long Chen; Zhao Zhang 010; Zhichun Zhu (PACT, 2011)

Conservative row activation to improve memory power efficiency. - Kun Fang 005; Zhichun Zhu (ICS, 2013)

Thermal Modeling and Management of DRAM Systems. - Jiang Lin; Hongzhong Zheng; Zhichun Zhu; Zhao Zhang 010 (IEEE Trans. Computers, 2013)

Access-Aware Memory Thermal Management. - Suyu Zhang; Zhichun Zhu (NAS, 2014)

Mini-Rank: A Power-EfficientDDRx DRAM Memory Architecture. - Kun Fang 005; Hongzhong Zheng; Jiang Lin; Zhao Zhang 010; Zhichun Zhu (IEEE Trans. Computers, 2014)

Refree: A Refresh-Free Hybrid DRAM/PCM Main Memory System. - Bahareh Pourshirazi; Zhichun Zhu (IPDPS, 2016)

NEMO: an energy-efficient hybrid main memory system for mobile devices. - Bahareh Pourshirazi; Zhichun Zhu (MEMSYS, 2017)

WALL: A writeback-aware LLC management for PCM-based main memory systems. - Bahareh Pourshirazi; Majed Valad Beigi; Zhichun Zhu; Gokhan Memik (DATE, 2018)

CAMPS: Conflict-Aware Memory-Side Prefetching Scheme for Hybrid Memory Cube. - Muhammad M. Rafique; Zhichun Zhu (ICPP, 2018)

FAPS-3D: feedback-directed adaptive page management scheme for 3D-stacked DRAM. - Muhammad M. Rafique; Zhichun Zhu (MEMSYS, 2019)

Writeback-Aware LLC Management for PCM-Based Main Memory Systems. - Bahareh Pourshirazi; Majed Valad Beigi; Zhichun Zhu; Gokhan Memik (ACM Trans. Design Autom. Electr. Syst., 2019)

DeepSwapper: A Deep Learning Based Page Swap Management Scheme for Hybrid Memory Systems. - Majed Valad Beigi; Bahareh Pourshirazi; Gokhan Memik; Zhichun Zhu (PACT, 2020)

POMI: Polling-Based Memory Interface for Hybrid Memory System. - Trung Le 003; Zhao Zhang 008; Zhichun Zhu (ICCD, 2021)

Memory-Side Prefetching Scheme Incorporating Dynamic Page Mode in 3D-Stacked DRAM. - Muhammad M. Rafique; Zhichun Zhu (IEEE Trans. Parallel Distributed Syst., 2021)

Dynamic Page Policy Using Perceptron Learning. - Muhammad M. Rafique; Zhichun Zhu (MEMSYS, 2022)

Redundant Array of Independent Memory Devices. - Peiyun Wu; Trung Le 003; Zhichun Zhu; Zhao Zhang 008 (IEEE Comput. Archit. Lett., 2023)

Polling-Based Memory Interface. - Trung Le 003; Zhao Zhang 008; Zhichun Zhu (ACM Trans. Design Autom. Electr. Syst., 2023)