Multibank memory optimization for parallel data access in multiple data arrays. - Shouyi Yin; Zhicong Xie; Chenyue Meng; Leibo Liu; Shaojun Wei (ICCAD, 2016)

Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM. - Shouyi Yin; Zhicong Xie; Shaojun Wei (DAC, 2017)

Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). - Tianyi Lu; Shouyi Yin; Xianqing Yao; Zhicong Xie; Leibo Liu; Shaojun Wei (FPGA, 2017)

Memory fartitioning-based modulo scheduling for high-level synthesis. - Tianyi Lu; Shouyi Yin; Xianqing Yao; Zhicong Xie; Leibo Liu; Shaojun Wei (ISCAS, 2017)

Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis. - Shouyi Yin; Tianyi Lu; Xianqing Yao; Zhicong Xie; Leibo Liu; Shaojun Wei (IEEE Access, 2018)

Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays. - Shouyi Yin; Zhicong Xie; Chenyue Meng; Peng Ouyang; Leibo Liu; Shaojun Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM. - Shouyi Yin; Tianyi Lu; Zhicong Xie; Leibo Liu; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2018)