A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference. - Wang Ye; Linfang Wang; Zhidao Zhou; Junjie An; Weizeng Li; Hanghang Gao; Zhi Li 062; Jinshan Yue; Hongyang Hu; Xiaoxin Xu; Jianguo Yang; Jing Liu 035; et al. (IEEE J. Solid State Circuits, 2023)

LIghtweight Texture-Guided Fast Partition Method for Luma and Chroma Intra Coding in VVC. - Zhikai Liu; Zhidao Zhou; Fan Liang; Wei Sun (ICME Workshops, 2024)

Cross-Frame Integrated Prediction for Feature-Space Video Compression. - Hongxin Qiu; Zhidao Zhou; Kai Lu; Fan Liang (IJCNN, 2024)

PFR-VC: Learning-Based Video Compression Framework with Predicted Frame Refinement. - Zhidao Zhou; Hongxin Qiu; Zhikai Liu; Wei Sun; Fan Liang (IJCNN, 2024)

A 2T P-Channel Logic Flash Cell for Reconfigurable Interconnection in Chiplet-Based Computing-In-Memory Accelerators. - Weizeng Li; Linfang Wang; Zhi Li 062; Wang Ye; Zhidao Zhou; Haiyang Zhou; Hanghang Gao; Jinshan Yue; Hongyang Hu; Fengman Liu; Qing Luo; Chunmeng Dou (ISCAS, 2024)

34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process. - Linfang Wang; Weizeng Li; Zhidao Zhou; Hanghang Gao; Zhi Li 062; Wang Ye; Hongyang Hu; Jing Liu 035; Jinshan Yue; Jianguo Yang; Qing Luo; Chunmeng Dou; et al. (ISSCC, 2024)

PFT-ILF: In-loop Filter with Partition Feature Transform for Versatile Video Coding. - Xin-Yi Cui; Zhikai Liu; Zhidao Zhou; Li Chen; Fan Liang (VCIP, 2024)

Multi-stage Attention Network with Auxiliary Information Refinement for VVC In-loop Filtering. - Xin-Yi Cui; Zhidao Zhou; Zhikai Liu; Li Chen; Fan Liang (VCIP, 2024)

Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge. - Junjie An; Zhidao Zhou; Linfang Wang; Wang Ye; Weizeng Li; Hanghang Gao; Zhi Li 062; Jinghui Tian; Yan Wang; Hongyang Hu; Jinshan Yue; Lingyan Fan; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2024)

An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree. - Wang Ye; Hanghang Gao; Zhidao Zhou; Linfang Wang; Weizeng Li; Zhi Li 062; Jinshan Yue; Xiaoxin Xu; Jianguo Yang; Hongyang Hu; Chunmeng Dou (IEEE Trans. Very Large Scale Integr. Syst., 2025)