Measurement-based stochastic modeling for co-existing propagation channels in cooperative relay scenarios. - Xuefeng Yin; Jingyi Liang; Yaoyao Fu; Jiwei Yu; Zhifeng Zhang 001; Jae Joon Park; Myung Don Kim; Hyun Kyu Chung (Future Network & Mobile Summit, 2012)

Parametric Modeling of the Cross-Correlation for Large-Scale-Fading of Propagation Channels. - Xuefeng Yin; Xu Zhou; Zhifeng Zhang 001; Myung Don Kim; Hyun Kyu Chung (VTC Spring, 2012)

Architecture and implementation of a vector MAC unit for complex number. - Yuan Luo; Zhifeng Zhang 001; Xin-Lin Huang; Jun Wu 006; Xin Chen 033 (ChinaCom, 2014)

Design and Implementation for GPU-based seamless rate adaptive decoder. - Lu Qiu; Min Wang 020; Jun Wu 006; Zhifeng Zhang 001; Xin-Lin Huang (ChinaCom, 2014)

On reliability requirement for BSM broadcast for safety applications in DSRC system. - Wenfeng Li; Jun Wu 006; Xiaomin Ma; Zhifeng Zhang 001 (Intelligent Vehicles Symposium, 2014)

Design and Implementation of Seamless Rate Adaptive Decoder. - Lu Qiu; Min Wang 020; Jun Wu 006; Zhifeng Zhang 001; Xinlin Huang (MILCOM, 2014)

An iterative interference cancellation design and analysis for uplink cooperation among base stations. - Zi Teng; Jun Wu 006; Xin-Lin Huang; Zhifeng Zhang 001 (WCSP, 2014)

A VLIW DSP for communication applications. - Haoqi Ren; Zhifeng Zhang 001; Jun Wu 006 (IGSC, 2015)

Cloud radio access network (C-RAN): a primer. - Jun Wu 006; Zhifeng Zhang 001; Yu Hong; Yonggang Wen 001 (IEEE Netw., 2015)

A Multi-mode Coordinate Rotation Digital Computer (CORDIC). - Lifan Niu; Xiaoling Jia; Jun Wu 006; Zhifeng Zhang 001 (ChinaCom (2), 2016)

FPGA-Based Turbo Decoder Hardware Accelerator in Cloud Radio Access Network (C-RAN). - Shaoxian Tang; Zhifeng Zhang 001; Jun Wu 006; Hui Zhu 012 (ChinaCom (1), 2016)

Scheduling Algorithm Design for Virtualized Hardware Accelerator in C-RAN. - Hui Zhu 012; Zhifeng Zhang 001; Jun Wu 006; Dong Guo; Shaoxian Tang (ICCCRI, 2016)

An ASIC Fast Decoder of Rate Compatible Modulation and Its Application in Wireless Communication System. - Wei Yu; Jun Wu 006; Hao Cui 001; Zhifeng Zhang 001; Haoqi Ren (MLICOM, 2016)

SWIFT: A Computationally-Intensive DSP Architecture for Communication Applications. - Haoqi Ren; Zhifeng Zhang 001; Jun Wu 006 (Mob. Networks Appl., 2016)

Historical Spectrum Sensing Data Mining for Cognitive Radio Enabled Vehicular Ad-Hoc Networks. - Xin-Lin Huang; Jun Wu 006; Wenfeng Li; Zhifeng Zhang 001; Fusheng Zhu; Minghao Wu (IEEE Trans. Dependable Secur. Comput., 2016)

DSP Implementation and Optimization of Pseudo Analog Video Transmission Algorithm. - Chengcheng Wang; Pengfei Xia; Haoqi Ren; Jun Wu 006; Zhifeng Zhang 001 (ChinaCom, 2018)

Toward a Network Slice Design for Ultra High Definition Video Broadcasting in 5G. - Bin Tan; Jianmin Lu; Jun Wu 006; Dongdong Zhang; Zhifeng Zhang 001 (IEEE Wirel. Commun., 2018)

Design and Implementation of Assembler for High Performance Digital Signal Processor (DSP). - Peng Ding; Haoqi Ren; Zhifeng Zhang 001; Jun Wu 006; Fusheng Zhu; Wenru Zhang (ChinaCom (1), 2019)

A High-Performance Systolic Array Accelerator Dedicated for CNN. - Jing Shen; Haoqi Ren; Zhifeng Zhang 001; Jun Wu 006; Wenqi Pan; Zhenyu Jiang (ICCT, 2019)

Reinforcement Learning Based Wireless Augmented Reality on Mobile Edge Computing. - Rui Qin; Dian Liu; Jun Wu 006; Fusheng Zhu; Haoqi Ren; Zhifeng Zhang 001 (ICII, 2019)

HARQ-Chaotic: Analog Chaotic Code Applied in HARQ Scheme of Wireless Communication System. - Wei Yu; Fusheng Zhu; Jun Wu 006; Rui Wang 001; Haoqi Ren; Zhifeng Zhang 001 (Wirel. Commun. Mob. Comput., 2019)

Efficient Architecture for Convolution and Softmax Function in Deep Learning Accelerator. - Zhenyu Jiang; Zhifeng Zhang 001; Haoqi Ren; Jun Wu 006 (ChinaCom, 2020)

A Deep Learning Compiler for Vector Processor. - Pingping Pan; Jun Wu 006; Songyuan Zhao; Haoqi Ren; Zhifeng Zhang 001 (ChinaCom, 2020)

A Real-time Virtual Reality Adaptive Streaming System. - Songyuan Zhao; Bin Tan; Jun Wu 006; Haoqi Ren; Zhifeng Zhang 001 (VTC Fall, 2020)

Design and Verification of High Performance Memory Interface Based on AXI Bus. - Ming Chen; Zhifeng Zhang 001; Haoqi Ren (ICCT, 2021)

Design and Implementation of DSP Cache. - Kunkun Liang; Jun Wu 006; Haoqi Ren; Zhifeng Zhang 001; Bin Tan (ICCT, 2021)

A Blockchain Based Automatic Access Scheme Design and Implement for Small Cell Base Station. - Jingchao Liang; Jun Wu 006; Bin Tan; Haoqi Ren; Zhifeng Zhang 001 (ICCT, 2021)

DSP Assembler Auto-Generation Technique and ToolChain Integration. - Wanli Wang; Jun Wu 006; Haoqi Ren; Zhifeng Zhang 001 (ICCT, 2021)

A Deep Image Coding Scheme With Generative Network to Learn From Correlated Images. - Yihao Chen; Bin Tan; Jun Wu 006; Zhifeng Zhang 001; Haoqi Ren (IEEE Trans. Multim., 2021)

A Low-Cost Semihosting Approach to Debug DSP Application. - Tao Huang; Haoqi Ren; Zhifeng Zhang 001; Bin Tan; Jun Wu 006 (ChinaCom, 2022)

An Efficient Memory Management Method for Embedded Vector Processors. - Shengxuan Li; Haoqi Ren; Zhifeng Zhang 001; Bin Tan; Jun Wu 006 (ChinaCom, 2022)

Optimization of Tensor Operation in Compiler. - Chenguang Qiu; Jun Wu 006; Haoqi Ren; Zhifeng Zhang 001 (ChinaCom, 2022)

A Reconfigurable Convolutional Neural Networks Accelerator Based on FPGA. - Yalin Tang; Haoqi Ren; Zhifeng Zhang 001 (ChinaCom, 2022)

An Efficient DSP Simulator Design Supporting Multi-Core Debugging. - Wentao Qiao; Jun Wu 006; Haoqi Ren; Zhifeng Zhang 001; Bin Tan (ICCT, 2023)

An Efficient and Secure Inline Assembly Design for VLIW DSP. - Hao Yu; Jun Wu 006; Haoqi Ren; Zhifeng Zhang 001; Bin Tan (ICCT, 2023)