Test Pattern Generation for Column Compression Multiplier. - Pingying Zeng; Zhigang Mao; Yizheng Ye; Yuliang Deng (Asian Test Symposium, 1998)

A New Algorithm for Retiming-Based Partial Scan. - Zulan Huang; Yizheng Ye; Zhigang Mao (Asian Test Symposium, 1999)

Implementation of Java Card Virtual Machine. - Liu Songyan; Zhigang Mao; Yizheng Ye (J. Comput. Sci. Technol., 2000)

An adaptive motion estimation algorithm based on evolution strategies. - Hui Wang; Zhigang Mao (ICASSP (3), 2004)

An adaptive motion estimation algorithm based on evolution strategies with correlated mutations. - Hui Wang; Zhigang Mao (ICIP, 2004)

Efficient frame-level pipelined array architecture for full-search block-matching motion estimation. - Weifeng He; Yunlong Bi; Zhigang Mao (ISCAS (3), 2005)

Design and VLSI Architecture of a Channel Equalizer Based on Adaptive Modulation for IEEE 802.11a WLAN. - Wei Zhong; Zhigang Mao (APCCAS, 2006)

Pareto based Multi-objective Mapping IP Cores onto NoC Architectures. - Wenbiao Zhou; Yan Zhang 066; Zhigang Mao (APCCAS, 2006)

A Restoration Algorithm for Images Contaminated by Impulse Noise. - Peng Liu; Yan Zhang 066; Zhigang Mao (J. Comput. Res. Dev., 2006)

Efficient time-domain residual ISI cancellation for OFDM-based WLAN systems. - Wei Zhong; Zhigang Mao (IEEE Trans. Consumer Electron., 2006)

A Link-Load Balanced Low Energy Mapping and Routing for NoC. - Wenbiao Zhou; Yan Zhang 066; Zhigang Mao (ICESS, 2007)

An Improved Frame-Level Pipelined Architecture for High Resolution Video Motion Estimation. - Wei-Feng He; Zhi-Gang Mao (ISCAS, 2007)

A Scalable Frame-Level Pipelined Architecture for FSBM Motion Estimation. - Wei-Feng He; Meng-Lian Zhao; Chi-Ying Tsui; Zhi-Gang Mao (VLSI Design, 2007)

An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling. - Weiguang Sheng; Liyi Xiao; Zhigang Mao (DELTA, 2008)

A Hybrid Anti-Collision Algorithm for RFID with Enhanced Throughput and Reduced Memory Consumption. - Majun Zheng; Jing Xie 010; Zhigang Mao; Yongxin Zhu 001 (EUC (1), 2008)

A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis. - Weiguang Sheng; Liyi Xiao; Zhigang Mao (ICECS, 2008)

Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns. - Weiguang Sheng; Liyi Xiao; Zhigang Mao (PRDC, 2008)

Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm. - Weiguang Sheng; Liyi Xiao; Zhigang Mao (DAC, 2009)

Statistical Estimation for Total Communication Load in Application-Specific Network-on-Chip. - Naifeng Jing; Zhigang Mao; Yongxin Zhu 001 (ICESS, 2009)

An efficient VLSI architecture for extended variable block sizes motion estimation. - Weifeng He; Weiwei Chen; Zhigang Mao (SoCC, 2010)

Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array. - Naifeng Jing; Weifeng He; Zhigang Mao (SoCC, 2010)

Conjugate Interleaved Partitioning PTS Scheme for PAPR Reduction of OFDM Signals. - Xin-chun Wu; Jinxiang Wang; Zhigang Mao; Jianwei Zhang 006 (Circuits Syst. Signal Process., 2010)

Statistical estimation and evaluation for communication mapping in Network-on-Chip. - Naifeng Jing; Weifeng He; Yongxin Zhu 001; Zhigang Mao (Integr., 2010)

A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications. - Jin Huang; Jing Xie 010; Zhigang Mao (ASICON, 2011)

A reconfigurable linear array processor architecture for data parallel and computation intensive applications. - Yucheng Liu; Jing Xie 010; Zhigang Mao (ASICON, 2011)

An efficient 90nm technology-node GHz transceiver of on-chip global interconnect. - Zaixiao Zheng; Zhigang Mao; Jianfei Jiang 001 (ASICON, 2011)

Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm. - Yifan Zhou; Weiguang Sheng; Xie Liu; Weifeng He; Zhigang Mao (ASICON, 2011)

Fault modeling and characteristics of SRAM-based FPGAs (abstract only). - Naifeng Jing; Ju-Yueh Lee; Chun Zhang; Jiarong Tong; Zhigang Mao; Lei He 001 (FPGA, 2011)

Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. - Naifeng Jing; Ju-Yueh Lee; Zhe Feng 002; Weifeng He; Zhigang Mao; Shi-Jie Wen; Rick Wong; Lei He 001 (FPL, 2011)

Mitigating FPGA interconnect soft errors by in-place LUT inversion. - Naifeng Jing; Ju-Yueh Lee; Weifeng He; Zhigang Mao; Lei He 001 (ICCAD, 2011)

A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme. - Xu Wang; Jianfei Jiang 001; Zhi-Gang Mao; Bingjing Ge; Xinglong Zhao (ICECS, 2011)

Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems. - Yuliang Tao; Guanghui He; Weifeng He; Qin Wang 009; Jun Ma 012; Zhigang Mao (ISCAS, 2011)

A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor. - Li Xie; Weifeng He; Naifeng Jing; Zhigang Mao (ISCAS, 2011)

Generalized interleaving network based on configurable QPP architecture for parallel turbo decoder. - Shuaijie Wang; Jun Ma 012; Guanghui He; Zhigang Mao (SiPS, 2011)

Parallel SFSD MIMO detection with SOFT-HARD combination enumeration. - Jianpeng Yu; Jun Ma 012; Zhigang Mao (SiPS, 2011)

A clock-less transceiver for global interconnect. - Jianfei Jiang 001; Xu Wang; Wei-Guang Sheng; Wei-Feng He; Zhi-Gang Mao (VLSI-SoC, 2011)

A 230mV 8-bit sub-threshold microprocessor for wireless sensor network. - Wei Jin 004; Sheng Lu; Weifeng He; Zhigang Mao (VLSI-SoC, 2011)

Robust design of sub-threshold flip-flop cells for wireless sensor network. - Wei Jin 004; Sheng Lu; Weifeng He; Zhigang Mao (VLSI-SoC, 2011)

A general statistical estimation for application mapping in Network-on-Chip. - Naifeng Jing; Weifeng He; Zhigang Mao (VLSI-SoC, 2011)

On-chip structure and addressing scheme design for 2-D block data processing in a 64-core array system. - Jing Xie 010; Huimin Xing; Zhigang Mao (VLSI-SoC, 2011)

Companding schemes based on transforming signal statistics into trigonal distributions for PAPR reduction in OFDM systems. - Xin-chun Wu; Jinxiang Wang; Bin Zhou; Zhigang Mao; Zhiqiang Gao (Int. J. Commun. Syst., 2011)

Low Complexity Time Domain Interleaved Partitioning Partial Transmit Sequence Scheme for Peak-to-Average Power Ratio Reduction of Orthogonal Frequency Division Multiplexing Systems. - Xin-chun Wu; Bin Zhou; Jinxiang Wang; Zhigang Mao (Wirel. Pers. Commun., 2011)

Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm. - Weiguang Sheng; Weifeng He; Jianfei Jiang 001; Zhigang Mao (IPDPS Workshops, 2012)

A pre-emphasis circuit design for high speed on-chip global interconnect. - Jianfei Jiang 001; Wei-Guang Sheng; Zhi-Gang Mao; Wei-Feng He (ISCAS, 2012)

Contention and energy aware mapping for real-time applications on Network-on-Chip. - Bingjing Ge; Naifeng Jing; Weifeng He; Zhigang Mao (ISOCC, 2012)

Novel O-GEHL Based Hyperblock Predictor for EDGE Architectures. - Pengfei Gou; Bing Yang; Mingyan Yu; Zhigang Mao (NAS, 2012)

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. - Naifeng Jing; Ju-Yueh Lee; Zhe Feng 002; Weifeng He; Zhigang Mao; Lei He 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor. - Haopeng Liu; Weiguang Sheng; Weifeng He; Zhigang Mao (ASICON, 2013)

TSVs-aware floorplanning for 3D integrated circuit. - Jieliang Lu; Qin Wang 009; Jing Xie 010; Zhigang Mao (ASICON, 2013)

A novel architecture scheme with adaptive pipeline coupling technique for DSP processor design. - Zheng Tang; Jing Xie 010; Zhigang Mao (ASICON, 2013)

A Block Cipher Circuit Design against Power Analysis. - Yuxiao Ling; Zheng Guo 001; Zhimin Zhang; Zhigang Mao; Zeleng Zhuang (CIS, 2013)

An energy-efficient and scalable eDRAM-based register file architecture for GPGPU. - Naifeng Jing; Yao Shen; Yao Lu; Shrikanth Ganapathy; Zhigang Mao; Minyi Guo; Ramon Canal; Xiaoyao Liang (ISCA, 2013)

A cost effective 2-D adaptive block size IDCT architecture for HEVC standard. - Liang Hong; Weifeng He; Hui Zhu; Zhigang Mao (MWSCAS, 2013)

Analysis of electromechanical interface model for liquid floated micro-gyroscope. - Mingyuan Ren; Xiaowei Liu; Wen Zuo; Zhigang Mao (NEMS, 2013)

A soft-output parallel stack algorithm for MIMO detection. - Zhi Yue; Guanghui He; Jiangpeng Li; Jun Ma 012; Zhigang Mao (SiPS, 2013)

A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard. - Liang Hong; Weifeng He; Hui Zhu; Zhigang Mao (IEICE Electron. Express, 2013)

Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs. - Jing Guo 004; Liyi Xiao; Zhigang Mao; Qiang Zhao (IEEE Micro, 2013)

Area and throughput efficient IDCT/IDST architecture for HEVC standard. - Ziyou Yao; Weifeng He; Liang Hong; Guanghui He; Zhigang Mao (ISCAS, 2014)

Improved Max-Log-MAP BICM-IDD receiver for MIMO systems. - Zhiting Yan; Guanghui He; Xi Chen; Weifeng He; Zhigang Mao (IEICE Electron. Express, 2014)

Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology. - Jing Guo 004; Liyi Xiao; Zhigang Mao (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code. - Jing Guo 004; Liyi Xiao; Zhigang Mao; Qiang Zhao (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Fault detection and redundancy design for TSVs in 3D ICs. - Sai Hu; Qin Wang 009; Zheng Guo 001; Jing Xie 010; Zhigang Mao (ASICON, 2015)

A crosstalk avoidance scheme based on re-layout of signal TSV. - Jiayi Hu; Qin Wang 009; Jianfei Jiang 001; Jing Xie 010; Zhigang Mao (ASICON, 2015)

Fault Secure Encoder and Decoder Designs for Matrix Codes. - Shanshan Liu 001; Liyi Xiao; Jing Guo 004; Zhigang Mao (CAD/Graphics, 2015)

Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs. - Naifeng Jing; Jiacheng Zhou; Jianfei Jiang 001; Xin Chen; Weifeng He; Zhigang Mao (ICCAD, 2015)

A contactless testing methodology for pre-bond interposer. - Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009; Zhigang Mao (MWSCAS, 2015)

Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework. - Weiguang Sheng; Zhongyuan Zhao 004; Zhigang Mao (PRDC, 2015)

Resource-saving compile flow for coarse-grained reconfigurable architectures. - Zhongyuan Zhao 004; Weiguang Sheng; Naifeng Jing; Weifeng He; Zhigang Mao (ReConFig, 2015)

Design optimization for capacitive-resistively driven on-chip global interconnect. - Jianfei Jiang 001; Weifeng He; Jizeng Wei; Qin Wang 009; Zhigang Mao (IEICE Electron. Express, 2015)

Improved Iterative Receiver for Co-channel Interference Suppression in MIMO-OFDM Systems. - Zhiting Yan; Guanghui He; Weifeng He; Zhigang Mao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing. - Zhiting Yan; Guanghui He; Yifan Ren; Weifeng He; Jianfei Jiang 001; Zhigang Mao (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Soft Error Hardened Memory Design for Nanoscale Complementary Metal Oxide Semiconductor Technology. - Jing Guo 004; Liyi Xiao; Tianqi Wang; Shanshan Liu 001; Xu Wang; Zhigang Mao (IEEE Trans. Reliab., 2015)

A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines. - Wei Jin 004; Seongjong Kim; Weifeng He; Zhigang Mao; Mingoo Seok (A-SSCC, 2016)

Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. - Naifeng Jing; Taozhong Li; Zhongyuan Zhao 004; Wei Jin 004; Yanan Sun 003; Weifeng He; Zhigang Mao (FPT, 2016)

Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding. - Liang Hong; Wei-Feng He; Guanghui He; Zhigang Mao (IEICE Electron. Express, 2016)

High performance parallel turbo decoder with configurable interleaving network for LTE application. - Zhiting Yan; Guanghui He; Weifeng He; Shuaijie Wang; Zhigang Mao (Integr., 2016)

Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. - Jianfei Jiang 001; Zhigang Mao; Weiguang Sheng; Qin Wang 009; Weifeng He (J. Circuits Syst. Comput., 2016)

Parallel SER analysis for combinational and sequential standard cell circuits. - Weiguang Sheng; Jianfei Jiang 001; Zhigang Mao (Microelectron. J., 2016)

Extend orthogonal Latin square codes for 32-bit data protection in memory applications. - Shanshan Liu 001; Liyi Xiao; Zhigang Mao (Microelectron. Reliab., 2016)

Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors. - Yanan Sun 003; Weifeng He; Zhigang Mao; Hailong Jiao; Volkan Kursun (ASICON, 2017)

Reliability analysis of memories suffering MBUs for the effect of negative bias temperature instability. - Shanshan Liu 001; Liyi Xiao; Xuebing Cao; Zhigang Mao (ASP-DAC, 2017)

A static-placement, dynamic-issue framework for CGRA loop accelerator. - Zhongyuan Zhao 004; Weiguang Sheng; Weifeng He; Zhigang Mao; Zhaoshi Li (DATE, 2017)

Low redundancy matrix-based codes for adjacent error correction with parity sharing. - Shanshan Liu 001; Liyi Xiao; Jie Li 030; Yihan Zhou; Zhigang Mao (ISQED, 2017)

A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras. - Wei Jin 004; Guanghui He; Weifeng He; Zhigang Mao (Integr., 2017)

Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC. - Qin Wang 009; Zhenyang Chen; Jianfei Jiang 001; Zheng Guo 001; Zhigang Mao (Integr., 2017)

Near- and Sub-Vt Pipelines Based on Wide-Pulsed-Latch Design Techniques. - Wei Jin 004; Seongjong Kim; Weifeng He; Zhigang Mao; Mingoo Seok (IEEE J. Solid State Circuits, 2017)

Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic. - Yanan Sun 003; Weifeng He; Zhigang Mao; Volkan Kursun (Microelectron. J., 2017)

Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology. - Jing Guo 004; Lei Zhu 004; Wenyi Liu; Hai Huang; Shanshan Liu 001; Tianqi Wang; Liyi Xiao; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2017)

In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations. - Wei Jin 004; Seongjong Kim; Weifeng He; Zhigang Mao; Mingoo Seok (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Optimizing the data placement and transformation for multi-bank CGRA computing system. - Zhongyuan Zhao 004; Yantao Liu; Weiguang Sheng; Tushar Krishna; Qin Wang 009; Zhigang Mao (DATE, 2018)

MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs. - Shuai Xie; Zhongyuan Zhao 004; Weiguang Sheng; Qin Wang 009; Zhigang Mao (ReConFig, 2018)

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications. - Jing Guo 004; Lei Zhu 004; Yu Sun; Huiliang Cao; Hai Huang; Tianqi Wang; Chunhua Qi; Rongsheng Zhang; Xuebing Cao; Liyi Xiao; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections. - Jiachen Jiang; Yanan Sun 003; Weifeng He; Zhigang Mao; Volkan Kursun (ASICON, 2019)

Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit. - Linzhe Li; Liyi Xiao; Jie Li 030; He Liu; Zhigang Mao (ASICON, 2019)

Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes. - Yanan Sun 003; Weifeng He; Zhigang Mao; Hailong Jiao; Volkan Kursun (ICEIC, 2019)

mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator. - Zhongyuan Zhao 004; Hyoukjun Kwon; Sachit Kuhar; Weiguang Sheng; Zhigang Mao; Tushar Krishna (ISPASS, 2019)

A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency. - Yongjie Lu; Yanan Sun 003; Weifeng He; Zhigang Mao (NANOARCH, 2019)

Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells. - Yanan Sun 003; Jiawei Gu; Weifeng He; Qin Wang 009; Naifeng Jing; Zhigang Mao; Weikang Qian; Li Jiang 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations. - Taozhong Li; Qin Wang 009; Yongxin Zhu 001; Jianfei Jiang 001; Guanghui He; Jing Jin 005; Zhigang Mao; Naifeng Jing (ACM Trans. Design Autom. Electr. Syst., 2019)

Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration. - Zihan Zhang; Taozhong Li; Ning Guan; Qin Wang 009; Guanghui He; Weiguang Sheng; Zhigang Mao; Naifeng Jing (ACM Great Lakes Symposium on VLSI, 2020)

25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip. - Chuxiong Lin; Weifeng He; Yanan Sun 003; Bingxi Pei; Zhigang Mao; Mingoo Seok (ISSCC, 2020)

Evaluating the influences of harvesting activity and eutrophication on loss of aquatic vegetations in Taihu Lake, China. - Juhua Luo; Ruiliang Pu; Hongtao Duan 001; Ronghua Ma; Zhigang Mao; Yuan Zeng; Linsheng Huang; Qitao Xiao (Int. J. Appl. Earth Obs. Geoinformation, 2020)

Mapping Long-Term Spatiotemporal Dynamics of Pen Aquaculture in a Shallow Lake: Less Aquaculture Coming along Better Water Quality. - Juhua Luo; Ruiliang Pu; Ronghua Ma; Xiaolong Wang; Xijun Lai; Zhigang Mao; Li Zhang; Zhaoliang Peng; Zhe Sun (Remote. Sens., 2020)

Priority Branches for Ship Detection in Optical Remote Sensing Images. - Yijia Zhang; Weiguang Sheng; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao (Remote. Sens., 2020)

Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density. - Yanan Sun 003; Weifeng He; Zhigang Mao; Hailong Jiao; Volkan Kursun (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling. - Zhongyuan Zhao 004; Weiguang Sheng; Qin Wang 009; Wenzhi Yin; Pengfei Ye; Jinchao Li; Zhigang Mao (IEEE Trans. Parallel Distributed Syst., 2020)

A Mapping Method for Reconfigurable Array based on Decoupled DataFlow. - Zihan Zhang; Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009; Zhigang Mao; Naifeng Jing (BigDataSecurity, 2021)

CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement. - Chuxiong Lin; Weifeng He; Yanan Sun 003; Zhigang Mao; Mingoo Seok (DAC, 2021)

Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture. - Yuge Chen; Zhongyuan Zhao 004; Jianfei Jiang 001; Guanghui He; Zhigang Mao; Weiguang Sheng (DATE, 2021)

Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. - Chen Yin; Qin Wang 009; Jianfei Jiang 001; Weiguang Sheng; Guanghui He; Zhigang Mao; Naifeng Jing (DATE, 2021)

Automatic Detection for Acromegaly Using Hand Photographs: A Deep-Learning Approach. - Chengbin Duan; Wenli Chen; Shun Yao; Zhigang Mao; Zongming Wang; Bin Hu; Haosen Jiao; Dimin Zhu; Yonghong Zhu; Haijun Wang (IEEE Access, 2021)

MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip. - Chuxiong Lin; Weifeng He; Yanan Sun 003; Bingxi Pei; Pavan Kumar Chundi; Zhigang Mao; Mingoo Seok (IEEE J. Solid State Circuits, 2021)

A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing. - Zhuojun Liang; Dongxu Lv; Chao Cui; Hai-Bao Chen; Weifeng He; Weiguang Sheng; Naifeng Jing; Zhigang Mao; Guanghui He (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits. - Linzhe Li; Liyi Xiao; He Liu; Zhigang Mao (IEEE Access, 2022)

A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images. - Guochao Deng; Qin Wang 009; Jianfei Jiang 001; Qirun Hong; Naifeng Jing; Weiguang Sheng; Zhigang Mao (IEEE Geosci. Remote. Sens. Lett., 2022)

A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM. - Taozhong Li; Naifeng Jing; Zhigang Mao; Yiran Chen 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator. - Zihan Zhang; Jianfei Jiang 001; Yongxin Zhu 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

MSLM-RF: A Spatial Feature Enhanced Random Forest for On-Board Hyperspectral Image Classification. - Shuai Yuan 016; Yanan Sun 003; Weifeng He; Qianrong Gu; Shi Xu; Zhigang Mao; Shikui Tu (IEEE Trans. Geosci. Remote. Sens., 2022)

A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator. - Taozhong Li; Naifeng Jing; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Yiran Chen 001 (ACM Trans. Design Autom. Electr. Syst., 2022)

An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs. - Shengzhao Li; Qin Wang 009; Jianfei Jiang 001; Weiguang Sheng; Naifeng Jing; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2022)

MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5. - Xiaoyan Li; Zizheng Dong; Shuaipeng Li; Sai Gao; Jianfei Jiang 001; Guanghui He; Zhigang Mao (ASICON, 2023)

An Efficient near-Bank Processing Architecture for Personalized Recommendation System. - Yuqing Yang; Weidong Yang; Qin Wang 009; Naifeng Jing; Jianfei Jiang 001; Zhigang Mao; Weiguang Sheng (ASP-DAC, 2023)

Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture. - Pengyu Liu 004; Zihan Zhang; Chen Yin; Liyan Chen; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (FPL, 2023)

A Hierarchical Communication Algorithm for Distributed Deep Learning Training. - Jiayu Zhang; Shaojun Cheng; Feng Dong; Ke Chen; Yong Qiao; Zhigang Mao; Jianfei Jiang 001 (MWSCAS, 2023)

RTMDet-R2: An Improved Real-Time Rotated Object Detector. - Haifeng Xiang; Naifeng Jing; Jianfei Jiang 001; Hongbo Guo; Weiguang Sheng; Zhigang Mao; Qin Wang 009 (PRCV (12), 2023)

A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration. - Chen Yin; Naifeng Jing; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Approximate Processing Element Design and Analysis for the Implementation of CNN Accelerators. - Tong Li; Honglan Jiang; Hai Mo; Jie Han 001; Leibo Liu; Zhi-Gang Mao (J. Comput. Sci. Technol., 2023)

BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars. - Yanan Sun 003; Zhi Li 058; Weiyi Liu; Weifeng He; Qin Wang 009; Zhigang Mao (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration. - Yuxuan Qin; Chuxiong Lin; Weifeng He; Yanan Sun 003; Zhigang Mao; Mingoo Seok (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture. - Liyan Chen; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (ASPDAC, 2024)

SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration. - Chen Yin; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (ASPDAC, 2024)

An Architectural Error Metric for CNN-Oriented Approximate Multipliers. - Ao Liu; Jie Han 001; Qin Wang 009; Zhigang Mao; Honglan Jiang (CoRR, 2024)

A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance. - Kunyue Li; Zhengji Zhao; Qixuan Cai; Qin Wang 009; Naifeng Jing; Zhigang Mao; Jianfei Jiang 001 (Expert Syst. Appl., 2024)

3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator. - Zihan Zhang; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating. - Chen Yin; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture. - Weidong Yang; Yuqing Yang; Shuya Ji; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao; Weiguang Sheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture. - Pengyu Liu 004; Ang Li; Liyan Chen; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

MDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory Processing. - Liyan Chen; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (ASP-DAC, 2025)

A Low-Power Mixed-Precision Integrated Multiply-Accumulate Architecture for Quantized Deep Neural Networks. - Xiaolu Hu; Xinkuang Geng; Zhigang Mao; Jie Han 001; Honglan Jiang (DATE, 2025)

HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler. - Weidong Yang; Shuya Ji; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao; Weiguang Sheng (DATE, 2025)

AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing. - Liyan Chen; Dongxu Lyu; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (HPCA, 2025)

L3: DIMM-PIM Integrated Architecture and Coordination for Scalable Long-Context LLM Inference. - Qingyuan Liu; Liyan Chen; Yanning Yang; Haocheng Wang; Dong Du 003; Zhigang Mao; Naifeng Jing; Yubin Xia; Haibo Chen 001 (CoRR, 2025)

A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip. - Zizheng Dong; Shuaipeng Li; Weijia Zhu; Ang Li; Qin Wang 009; Naifeng Jing; Weiguang Sheng; Jianfei Jiang 001; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Bridge-NDP: Efficient Communication-Computation Overlap in Near Data Processing System. - Liyan Chen; Pengyu Liu 004; Dongxu Lyu; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

MACS: A Multidomain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators. - Shuya Ji; Weidong Yang; Jianfei Jiang 001; Naifeng Jing; Honglan Jiang; Zhigang Mao; Qin Wang 009 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

A novel method for screening malignant hematological diseases by constructing an optimal machine learning model based on blood cell parameters. - Dehua Sun; Wei Chen; Jun He; Yongjian He; Haoqin Jiang; Hong Jiang; Dandan Liu; Lu Li; Min Liu; Zhigang Mao; Chenxue Qu; Linlin Qu; et al. (BMC Medical Informatics Decis. Mak., 2025)