Compiling to FPGAs via an EPIC compiler's intermediate representation. - Zhiguo Ge; Jirong Liao; Weng-Fai Wong (FPT, 2003)

A Reconfigurable Instruction Memory Hierarchy for Embedded Systems. - Zhiguo Ge; Hock-Beng Lim; Weng-Fai Wong (FPL, 2005)

DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems. - Zhiguo Ge; Weng-Fai Wong; Hock-Beng Lim (DATE, 2007)

A DVS-based pipelined reconfigurable instruction memory. - Zhiguo Ge; Tulika Mitra; Weng-Fai Wong (DAC, 2009)

SelectDirectory: a selective directory for cache coherence in many-core architectures. - Yuan Yao 006; Guanhua Wang; Zhiguo Ge; Tulika Mitra; Wenzhi Chen; Naxin Zhang (DATE, 2015)

Efficient Timestamp-Based Cache Coherence Protocol for Many-Core Architectures. - Yuan Yao 006; Guanhua Wang; Zhiguo Ge; Tulika Mitra; Wenzhi Chen; Naxin Zhang (ICS, 2016)