PEDSA: High-Throughput Pipeline-Based FPGA Accelerator for Convolutional Encoder-Decoder Segmentation Networks. - Yuxian Jiang; Zhan Li; Zhihan Zhang 004; Hao Wang 046; Sheng Chang 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

A High-Performance Pixel-Level Fully Pipelined Hardware Accelerator for Neural Networks. - Zhan Li; Zhihan Zhang 004; Jie Hu 044; Qunkang Meng; Xingyu Shi; Jun Luo; Hao Wang 046; Qijun Huang; Sheng Chang 003 (IEEE Trans. Neural Networks Learn. Syst., 2025)

A High-Intensity Solution of Hardware Accelerator for Sparse and Redundant Computations in Semantic Segmentation Models. - Jiahui Huang; Zhan Li; Yuxian Jiang; Zhihan Zhang 004; Hao Wang 046; Sheng Chang 003 (IEEE Trans. Computers, 2025)

MetaAccel: A High-Performance and Agile Accelerator Design Framework With Multi Clock Domain Optimization for Complex CNN. - Zhan Li; Yuxian Jiang; Zhihan Zhang 004; Jiahui Huang; Qunkang Meng; Xingyu Shi; Hao Wang 046; Qijun Huang; Sheng Chang 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2026)

Single-Step Hardware-Aware Neural Network Quantization With Mixed Precision. - Jie Hu 044; Zhihan Zhang 004; Zhan Li; Qunkang Meng; Xingyu Shi; Qijun Huang; Hao Wang 046; Sheng Chang 003 (IEEE Trans. Computers, 2026)