A 10T SRAM with Two Read and Write Modes across Row and Column for CAM Operation and Computing In-Memory. - Zhang Zhang 004; Zhihao Chen 008; Sikai Chen; Guangjun Xie; Jianmin Zeng; Gang Liu (ISCAS, 2024)

An oscillator replica bitline technique for suppressing timing variation of SRAM sense amplifiers. - Dekai Sun; Zhihao Chen 008; Sikai Chen; Zhang Zhang 004 (IEICE Electron. Express, 2025)

Reconfigurable 10T SRAM for Energy-Efficient CAM Operation and In-Memory Computing. - Zhang Zhang 004; Zhihao Chen 008; Jiedong Wang; Guangjun Xie; Gang Liu (IEEE Trans. Very Large Scale Integr. Syst., 2025)