15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization. - Ruiqi Guo; Zhiheng Yue; Xin Si; Te Hu; Hao Li; Limei Tang; Yabing Wang; Leibo Liu; Meng-Fan Chang; Qiang Li 021; Shaojun Wei; Shouyi Yin (ISSCC, 2021)

MC-CIM: a reconfigurable computation-in-memory for efficient stereo matching cost computation. - Zhiheng Yue; Yabing Wang; Leibo Liu; Shaojun Wei; Shouyi Yin (DAC, 2022)

BR-CIM: An Efficient Binary Representation Computation-In-Memory Design. - Zhiheng Yue; Yabing Wang; Yubin Qin; Leibo Liu; Shaojun Wei; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Systolic Computing-in-Memory Array based Accelerator with Predictive Early Activation for Spatiotemporal Convolutions. - Xiaofeng Chen; Ruiqi Guo; Zhiheng Yue; Yang Hu 001; Leibo Liu; Shaojun Wei; Shouyi Yin (AICAS, 2023)

CV-CIM: A 28nm XOR-Derived Similarity-Aware Computation-in-Memory for Cost-Volume Construction. - Zhiheng Yue; Yang Wang 089; Huizheng Wang; Yabing Wang; Ruiqi Guo; Limei Tang; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2023)

A 28nm 77.35TOPS/W Similar Vectors Traceable Transformer Processor with Principal-Component-Prior Speculating and Dynamic Bit-wise Stationary Computing. - Yang Wang 089; Yubin Qin; Dazheng Deng; Xiaolong Yang; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Leibo Liu; Shaojun Wei; Yang Hu 001; Shouyi Yin (VLSI Technology and Circuits, 2023)

STAR: An STGCN ARchitecture for Skeleton-Based Human Action Recognition. - Weiwei Wu; Fengbin Tu; Mengqi Niu; Zhiheng Yue; Leibo Liu; Shaojun Wei; Xiangyu Li; Yang Hu 001; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization. - Ruiqi Guo; Zhiheng Yue; Xin Si; Hao Li; Te Hu; Limei Tang; Yabing Wang; Hao Sun; Leibo Liu; Meng-Fan Chang; Qiang Li 021; Shaojun Wei; et al. (IEEE J. Solid State Circuits, 2023)

A 28nm 118.26TOPS/W Multi-Dimensional Fault-Tolerant Al Processor Enabling Voltage-Frequency Scaling Below Point-of-First-Failure. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Shaojun Wei; Yang Hu 001; Shouyi Yin (A-SSCC, 2024)

Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. - Xujiang Xiang; Zhiheng Yue; Yuxuan Li; Liuxin Lv; Shaojun Wei; Yang Hu 001; Shouyi Yin (DAC, 2024)

CAP: A General Purpose Computation-in-memory with Content Addressable Processing Paradigm. - Zhiheng Yue; Shaojun Wei; Yang Hu 001; Shouyi Yin (DAC, 2024)

Exploiting Similarity Opportunities of Emerging Vision AI Models on Hybrid Bonding Architecture. - Zhiheng Yue; Huizheng Wang; Jiahao Fang; Jinyi Deng; Guangyang Lu; Fengbin Tu; Ruiqi Guo; Yuxuan Li; Yubin Qin; Yang Wang 089; Chao Li 009; Huiming Han; et al. (ISCA, 2024)

20.2 A 28nm 74.34TFLOPS/W BF16 Heterogenous CIM-Based Accelerator Exploiting Denoising-Similarity for Diffusion Models. - Ruiqi Guo; Lei Wang; Xiaofeng Chen; Hao Sun; Zhiheng Yue; Yubin Qin; Huiming Han; Yang Wang 089; Fengbin Tu; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2024)

34.1 A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2024)

15.1 A 0.795fJ/bit Physically-Unclonable Function-Protected TCAM for a Software-Defined Networking Switch. - Zhiheng Yue; Xujiang Xiang; Fengbin Tu; Yang Wang 089; Yiming Wang; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2024)

SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling. - Huizheng Wang; Jiahao Fang; Xinru Tang; Zhiheng Yue; Jinxi Li; Yubin Qin; Sihan Guan; Qinze Yang; Yang Wang 089; Chao Li 009; Yang Hu 001; Shouyi Yin (MICRO, 2024)

A 22nm 54.94TFLOPS/W Transformer Fine-Tuning Processor with Exponent-Stationary Re-Computing, Aggressive Linear Fitting, and Logarithmic Domain Multiplicating. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (VLSI Technology and Circuits, 2024)

Efficient Orchestrated AI Workflows Execution on Scale-out Spatial Architecture. - Jinyi Deng; Xinru Tang; Zhiheng Yue; Guangyang Lu; Qize Yang; Jiahao Zhang; Jinxi Li; Chao Li 009; Shaojun Wei; Yang Hu 001; Shouyi Yin (CoRR, 2024)

SOFA: A Compute-Memory Optimized Sparsity Accelerator via Cross-Stage Coordinated Tiling. - Huizheng Wang; Jiahao Fang; Xinru Tang; Zhiheng Yue; Jinxi Li; Yubin Qin; Sihan Guan; Qize Yang; Yang Wang 089; Chao Li 009; Yang Hu 001; Shouyi Yin (CoRR, 2024)

14.4 A 51.6TFLOPs/W Full-Datapath CIM Macro Approaching Sparsity Bound and <-30 Loss for Compound AI. - Zhiheng Yue; Xujiang Xiang; Yang Wang 089; Ruiqi Guo; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (ISSCC, 2025)

A 28-nm 28.8-TOPS/W Attention-Based NN Processor With Correlative CIM Ring Architecture and Dataflow-Reshaped Digital-Assisted CIM Array. - Ruiqi Guo; Zhiheng Yue; Yang Wang 089; Hao Li; Te Hu; Yabing Wang; Hao Sun; Jeng-Long Hsu; Yaojun Zhang; Bonan Yan; Leibo Liu; Ru Huang 001; et al. (IEEE J. Solid State Circuits, 2025)

CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction. - Zhiheng Yue; Yang Wang 089; Huizheng Wang; Ruiqi Guo; Fengbin Tu; Jianxun Yang; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE J. Solid State Circuits, 2025)

Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. - Xujiang Xiang; Zhiheng Yue; Xiaolong Zhang; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications. - Yang Wang 089; Xiaolong Yang; Yubin Qin; Zhiren Zhao; Ruiqi Guo; Zhiheng Yue; Huiming Han; Shaojun Wei; Yang Hu 001; Shouyi Yin (IEEE J. Solid State Circuits, 2025)