SoC Leakage Power Reduction Algorithm by Input Vector Control. - Xiaotao Chang; Dongrui Fan; Yinhe Han 001; Zhimin Zhang 004 (SoC, 2005)

POSTER: An Optimization of Dataflow Architectures for Scientific Applications. - Xiaowei Shen; Xiaochun Ye; Xu Tan 001; Da Wang; Zhimin Zhang 004; Dongrui Fan; Zhimin Tang (PACT, 2016)

Memory partition for SIMD in streaming dataflow architectures. - Xiaowei Shen; Xiaochun Ye; Xu Tan 001; Da Wang; Zhimin Zhang 004; Zhimin Tang; Dongrui Fan (IGSC, 2016)

A framework for energy-efficient optimization on multi-cores. - Yatao Zhu; Xiaochun Ye; Da Wang; Wenming Li; Yang Zhang; Dongrui Fan; Zhimin Zhang 004; Zhimin Tang (IGSC, 2016)

An energy-efficient bandwidth allocation method for single-chip heterogeneous processor. - Yatao Zhu; Shuai Zhang; Xiaochun Ye; Da Wang; Xu Tan 001; Dongrui Fan; Zhimin Zhang 004; Hongliang Li (IGSC, 2016)

An Efficient Network-on-Chip Router for Dataflow Architecture. - Xiaowei Shen; Xiaochun Ye; Xu Tan 001; Da Wang; Lunkai Zhang; Wenming Li; Zhimin Zhang 004; Dongrui Fan; Ninghui Sun (J. Comput. Sci. Technol., 2017)

WEAVER: An Energy Efficient, General-Purpose Acceleration Architecture for String Operations in Big Data Applications. - Wenming Li; Xiaochun Ye; Da Wang; Hao Zhang 009; Dongdong Wu; Zhimin Zhang 004; Dongrui Fan (ISPA/IUCC/BDCloud/SocialCom/SustainCom, 2018)

High-Performance and Energy-Efficient Fault Tolerance Scheduling Algorithm Based on Improved TMR for Heterogeneous System. - Shigan Yu; Zhimin Tang; Xiaochun Ye; Zhimin Zhang 004; Dongrui Fan; Zhiying (ISPA/IUCC/BDCloud/SocialCom/SustainCom, 2018)

A Non-Stop Double Buffering Mechanism for Dataflow Architecture. - Xu Tan 001; Xiaowei Shen; Xiaochun Ye; Da Wang; Dongrui Fan; Lunkai Zhang; Wenming Li; Zhimin Zhang 004; Zhimin Tang (J. Comput. Sci. Technol., 2018)

iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack. - Kuozhong Zhang; Junying Huang; Jing Ye 001; Xiaochun Ye; Da Wang; Dongrui Fan; Huawei Li 001; Xiaowei Li 001; Zhimin Zhang 004 (IOLTS, 2019)

Balancing Memory Accesses for Energy-Efficient Graph Analytics Accelerators. - Mingyu Yan; Xing Hu 001; Shuangchen Li; Itir Akgun; Han Li 011; Xin Ma; Lei Deng 003; Xiaochun Ye; Zhimin Zhang 004; Dongrui Fan; Yuan Xie 001 (ISLPED, 2019)

Instruction Vulnerability Test and Code Optimization Against DVFS Attack. - Junying Huang; Jing Ye 001; Xiaochun Ye; Da Wang; Dongrui Fan; Huawei Li 001; Xiaowei Li 001; Zhimin Zhang 004 (ITC-Asia, 2019)

Alleviating Irregularity in Graph Analytics Acceleration: a Hardware/Software Co-Design Approach. - Mingyu Yan; Xing Hu 001; Shuangchen Li; Abanti Basak; Han Li 011; Xin Ma; Itir Akgun; Yujing Feng; Peng Gu; Lei Deng 003; Xiaochun Ye; Zhimin Zhang 004; et al. (MICRO, 2019)

Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits. - Rongliang Fu; Zhimin Zhang 004; Guang-Ming Tang; Junying Huang; Xiaochun Ye; Dongrui Fan; Ninghui Sun (ACM Great Lakes Symposium on VLSI, 2020)

HyGCN: A GCN Accelerator with Hybrid Architecture. - Mingyu Yan; Lei Deng 003; Xing Hu 001; Ling Liang; Yujing Feng; Xiaochun Ye; Zhimin Zhang 004; Dongrui Fan; Yuan Xie 001 (HPCA, 2020)

Characterizing and Understanding GCNs on GPU. - Mingyu Yan; Zhaodong Chen; Lei Deng 003; Xiaochun Ye; Zhimin Zhang 004; Dongrui Fan; Yuan Xie 001 (IEEE Comput. Archit. Lett., 2020)

Equivalence Checking for Superconducting RSFQ Logic Circuits. - Rongliang Fu; Junying Huang; Zhimin Zhang 004 (ACM Great Lakes Symposium on VLSI, 2021)

JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits. - Xinda Chen; Rongliang Fu; Junying Huang; Huawei Cao; Zhimin Zhang 004; Xiaochun Ye; Tsung-Yi Ho; Dongrui Fan (ACM Great Lakes Symposium on VLSI, 2023)

Characterizing and Understanding Defense Methods for GNNs on GPUs. - Meng Wu 006; Mingyu Yan; Xiaocheng Yang; Wenming Li; Zhimin Zhang 004; Xiaochun Ye; Dongrui Fan (IEEE Comput. Archit. Lett., 2023)

Design of a Compact Superconducting RSFQ Register File. - Kuozhong Zhang; Zhimin Zhang 004; Guang-Ming Tang; Xiaochun Ye (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. - Siyan Chen; Rongliang Fu; Junying Huang; Zhimin Zhang 004; Xiaochun Ye; Tsung-Yi Ho; Dongrui Fan (DATE, 2024)

Accelerating Mini-batch HGNN Training by Reducing CUDA Kernels. - Meng Wu 006; Jingkai Qiu; Mingyu Yan; Wenming Li; Yang Zhang; Zhimin Zhang 004; Xiaochun Ye; Dongrui Fan (ICA3PP (3), 2024)