Dynamically Reconfigurable Neuron Architecture for the Implementation of Self-Organizing Learning Array. - Janusz A. Starzyk; Yongtao Guo; Zhineng Zhu (IPDPS, 2004)

A Low-noise Low-offset Op Amp in 0.35μm CMOS Process. - Zhineng Zhu; Raghu Tumati; Scott D. Collins; Rosemary L. Smith; David E. Kotecki (ICECS, 2006)

Dynamically reconfigurable neuron architecture for the implementation of self-organising learning array. - Janusz A. Starzyk; Yongtao Guo; Zhineng Zhu (Int. J. Embed. Syst., 2006)

Self-organizing learning array and its application to economic and financial problems. - Zhineng Zhu; Haibo He; Janusz A. Starzyk; C. Tseng (Inf. Sci., 2007)