Pipelined QR decomposition based multi-channel least square lattice adaptive filter architectures. - Zhipei Chi; Jun Ma; Keshab K. Parhi (ISCAS (3), 1999)

High throughput low energy FEC/ARQ technique for short frame turbo codes. - Zhipei Chi; Zhongfeng Wang 001; Keshab K. Parhi (ICASSP, 2000)

A study on the performance, power consumption tradeoffs of short frame turbo decoder design. - Zhipei Chi; Zhongfeng Wang 001; Keshab K. Parhi (ICASSP, 2001)

Area-efficient high speed decoding schemes for turbo/MAP decoders. - Zhongfeng Wang 001; Zhipei Chi; Keshab K. Parhi (ICASSP, 2001)

A study on the performance, complexity tradeoffs of block turbo decoder design. - Zhipei Chi; Leilei Song; Keshab K. Parhi (ISCAS (4), 2001)

High speed algorithm and VLSI architecture design for decoding BCH product codes. - Zhipei Chi; Keshab K. Parhi (ICASSP, 2002)

High speed VLSI architecture design for block turbo decoder. - Zhipei Chi; Keshab K. Parhi (ISCAS (1), 2002)

Area-efficient high-speed decoding schemes for turbo decoders. - Zhongfeng Wang 001; Zhipei Chi; Keshab K. Parhi (IEEE Trans. Very Large Scale Integr. Syst., 2002)

On The Performance/Complexity Tradeoff in Block Turbo Decoder Design. - Zhipei Chi; Leilei Song; Keshab K. Parhi (IEEE Trans. Commun., 2004)

On the better protection of short-frame turbo codes. - Zhipei Chi; Zhongfeng Wang 001; Keshab K. Parhi (IEEE Trans. Commun., 2004)